Fault Diagnosis of Electronic Circuits Using Cellular Automata Based Pattern Classifier
This chapter formulates fault diagnosis in electronic circuits as a pattern classification problem. The proposed pattern classification scheme employs the computing model of a special class of sparse network referred to as cellular automata (CA). A partic
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Machine Intelligence Unit, Indian Statistical Institute, Kolkata, India [email protected] Cellular Automata Research Laboratory, Rajarhat Megacity, Kolkata, India [email protected]
1 Introduction This chapter formulates fault diagnosis in electronic circuits as a pattern classification problem. The proposed pattern classification scheme employs the computing model of a special class of sparse network referred to as cellular automata (CA). A particular class of CA referred to as multiple attractor CA (MACA) has been projected as a classifier of faulty response-pattern of a circuit. The genetic algorithm (GA) is employed to synthesize the desired CA required for diagnosis of a circuit under test (CUT). The CUT is assumed to have a network of large number of circuit components partitioned into a number of sub-circuits referred to as modules. Introduction of GA significantly reduces the design overhead of the MACA based classifier that supports: 1. low memory overhead for diagnosis - reduction of one to two order of magnitude of memory overhead has been achieved over that required for conventional fault dictionary based diagnosis scheme; 2. excellent diagnostic resolution and low diagnostic aliasing; and 3. low cost hardware of a generic fault diagnosis machine (FDM) with simple, regular, modular, and cascadable structure of CA that suits ideally for very large scale integration (VLSI) implementation. Thus, the FDM can be viewed as a Watch-Dog Processor intended for high speed on-line diagnosis for critical application areas. The following scenario motivated us to undertake this research. In order to improve the product quality, reduce time to market, and cut down production cost, the demand for fault diagnosis in an electronic circuit has greatly increased. The objective of fault diagnosis is to guide the test engineers to search the physical location of the defect on a circuit in the early production phase. Use of fault dictionaries is a probable solution for the diagnosis process, particularly when repeated diagnosis is required for different copies of the same circuit [1, 2, 3]. But this scheme becomes inefficient for a sufficiently large circuit due to the large volume of fault dictionary. Different schemes to compact the size of the dictionary are addressed in [4, 5, 6]. However, such compaction reduces B. Prasad (Ed.): Soft Computing Applications in Industry, STUDFUZZ 226, pp. 225–246, 2008. c Springer-Verlag Berlin Heidelberg 2008 springerlink.com
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P. Maji and P.P. Chaudhuri
diagnostic resolution since multiple response patterns for different faults get compressed to the identical signature. The best test environment for diagnostic purposes should differentiate between all faults that are distinguishable. In the above background, we propose an efficient fault diagnosis scheme to identify a defect down to a set of candidate locations referred to as faulty module of an electronic circuit. Both analog and digital circuits can be handled by this scheme. The diagnosis scheme employs two class classifier designed wi
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