Ferroelectric devices and circuits for neuro-inspired computing
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Prospective Article
Ferroelectric devices and circuits for neuro-inspired computing Panni Wang GA 30332, USA
and Shimeng Yu, School of Electrical and Computer Engineering, Georgia Institute of Technology, 791 Atlantic Dr NW, Atlanta,
Address all correspondence to Shimeng Yu at [email protected] (Received 25 June 2020; accepted 10 September 2020)
Abstract Recent discovery of ferroelectricity in doped HfO2 has reignited research interest in the ferroelectric field-effect transistor (FeFET) as emerging embedded nonvolatile memory with the potential for neuro-inspired computing. This paper reviews two major aspects for its application in neuro-inspired computing: ferroelectric devices as multilevel synaptic devices and the circuit primitive design with FeFET for in-memory computing. First, the authors survey representative FeFET-based synaptic devices. Then, the authors introduce 2T-1FeFET synaptic cell design that improves its in situ training accuracy to approach software baseline. Then, the authors introduce the FeFET drain–erase scheme for array-level operations, which makes the in situ training feasible for FeFET-based hardware accelerator. Finally, the authors give an outlook on the future 3D-integrated 2T-1FeFET design.
Introduction Deep neural networks (DNNs) have obtained significant improvements in accuracy on various large-scale classification and recognition tasks, some even surpassing human-level performance.[1] However, to improve the training accuracy for the DNNs model, the DNNs model’s parameters grow exponentially leading to hundreds of millions of parameters and enormous training datasets to be stored in the memory. In tradition, in the von Neumann-based computer architecture, the data need to be moved back and forth between the memory and the processor, which limits the hardware energy efficiency as the data traffic is extensive in these machine learning workloads. In-memory computing, where the computation is performed directly in the memory location, reduced the energy and latency for data movement, thus accelerating the DNNs inference and training process. Toward the neuro-inspired computing, various memory candidates such as static randomaccess memory (SRAM)[2] and emerging nonvolatile memories (eNVMs) including phase-change memory (PCM)[3,4] and resistive random-access memory (RRAM)[5–8] have been explored for application in both inference and in situ training. However, SRAM is suffering from increasing leakage power and low integration density restricting its application in the large-scale neural network. New hardware requirements such as low standby power and high integration density to satisfy the data-centric computing have led to a research focus on eNVMs.[9] PCM and RRAM are both two-terminal devices. Despite the simple structure at a first glance, a memory-only crossbar array suffers from sneak path issue. While the twoterminal selectors can potentially solve this problem, the technology for the two-terminal selector is still premature.[10]
Therefore, the two-terminal memory devic
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