Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps
- PDF / 2,328,261 Bytes
- 12 Pages / 612 x 792 pts (letter) Page_size
- 89 Downloads / 270 Views
B10.1.1
Flip Chip Reliability of GaAs on Si Thinfilm Substrates Using AuSn Solder Bumps Hermann Oppermann, Matthias Hutter, Matthias Klein, Gunter Engelmann, Michael Toepper, and Jürgen Wolf Fraunhofer IZM, Gustav-Meyer-Allee 25, D-13355 Berlin, Germany [email protected]; phone: +49 30 46403-163, fax: +49 30 46403-162 ABSTRACT Au/Sn solder bumps are mainly used for flip chip assembly of compound semiconductors in optoelectronic and RF applications. They allow a fluxless assembly which is required to avoid contamination of optical interfaces and the metallurgy is well suited to the final gold metallization on GaAs or InP. Flip chip assembly experiments were carried out using two layer Au/Sn bumps as plated without prior bump reflow. An RF and reliability test vehicles comprise a GaAs chip which was flip chip soldered on a silicon substrate. Temperature cycling tests with and without underfiller were performed. The different failure modes for underfilled and nonunderfilled samples were discussed and compared. Additional reliability tests were performed with flip chip bonding by gold thermocompression for comparison. The test results and the failure modes are discussed in detail. Keywords: Au-Sn, gold-tin, AuSn, solder, bumping, flip chip, fluxless, gold, thermocompression bonding, GaAs, thinfilm substrate, reliability, underfiller 1. INTRODUCTION The assembly of optoelectronic components requires fluxless processes like Au/Sn solder to avoid the contamination of optical interfaces. Au/Sn solder is suitable to be processed fluxless and it is favored due to the potential of self-alignment of components in the soldering step. In addition the solder is very hard, therefore no plastic deformation, creep or relaxation is expected. Flip chip is advantageous for RF applications as they have very low electrical parasitic capacitance and inductance due to the short interconnect from chip to module. The AuSn solder alloy is suitable for thick gold metallization used as top metal on chip and RF substrates. Therefore it seems very likely to use Au/Sn solder bumps for flip chip interconnect. The bumps discussed are manufactured by electroplating gold and tin in subsequent process steps [1]. After the plating process the bumps consist of a thick gold layer and a thinner Sn layer on top (Figure 1). When the bumps are heated up to above 280°C a solder cap forms which consists of the eutectic microstructure with the composition of 80 wt.-% Au and 20 wt.-% Sn. After this process step, which is called bump reflow, the bumps consist of a Au layer with an eutectic solder cap on top (Figure 2). The Au layer which appears like a socket in cross section and the eutectic solder cap are separated by a layer of intermetallic Au5Sn-phase which is referred to as ζ-phase in the following. During flip chip assembly the eutectic part melts while the rest of the bump remains solid [2, 3].
B10.1.2
Figure 1: Small Au/Sn bump for InP photodetector
Figure 2. Cross section SEM image of a Au/Sn bump of 50 µm in diameter after reflow.
Data Loading...
