Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy
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Fundamental Limits for 3D Wafer-to-Wafer Alignment Accuracy M. Wimplinger, J.-Q. Lu*, J. Yu*, Y. Kwon*, T. Matthias**, T.S. Cale*, and R.J. Gutmann* EV Group Inc., 3701 E. University Dr., Phoenix, AZ 85034, [email protected] *Rensselaer Polytechnic Institute, 110 8th Street, Troy, NY 12180, [email protected] ** EV Group, E. Thallner Str. 1, 4780 Schaerding, Austria ABSTRACT Wafer-level three-dimensional (3D) integration as an emerging architecture for future chips offers high interconnect performance by reducing delays of global interconnects and high functionality with heterogeneous integration of materials, devices, and signals. Various 3D technology platforms have been investigated, with different combinations of alternative alignment, bonding, thinning and inter-wafer interconnection technologies. Precise alignment on the wafer level is one of the key challenges affecting the performance of the 3D interconnects. After a brief overview of the wafer-level 3D technology platforms, this paper focuses on waferto-wafer alignment fundamentals. Various alignment methods are reviewed. A higher emphasis lies on the analysis of the alignment accuracy. In addition to the alignment accuracy achieved prior to bonding, the impacts of wafer bonding and subsequent wafer thinning will be discussed. INTRODUCTION It is an acknowledged fact in the IC industry, that one of the major challenges for further enhancing Moore’s law will be Interconnect Technology [1-3]. 3D Interconnect using wafer-towafer chip stacking offers an approach to vertically connect two integrated circuits for the purpose of shortening the wiring distance between them. Wafers are aligned, bonded, and interconnected face-to-face, then thinned-back prior to dicing. The most critical challenge in interconnect technology are the so-called “global” interconnects, that are routed across the whole chip and distribute time critical signals. Prominent examples for that are “clock distribution” trees and the communication lines with e.g. an on–chip memory. [2-4] Stacking of functional modules such as logic and memory or logic and sensing element reduces the length of these critical connections from millimeters or centimeters to a couple of microns. That reduction of the interconnect length by orders of magnitude reduces the interconnect related delays in these lines by the same factor. Besides this tremendous advantage, 3 D integration also offers additional advantages: Today’s high performance microprocessors include a huge on-chip memory. In many cases, this memory is as big as the logic part of the processor itself. 3 D integration will allow for manufacture of the memory on a separate wafer with optimised processing. (E.g., the wafer only needs to be processed through the mask levels that are required to manufacture the memory) This will allow for a more cost effective manufacturing process at higher yields. This integration of modules produced with optimised processes can be even further expanded to the integration of dissimilar substrate materials. This is
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