GaN HEMT Drain-Lag Performance Dependence on GaN Channel Quality
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GaN HEMT Drain-Lag Performance Dependence on GaN Channel Quality Yoichi Kamada, Naoya Okamoto, Masaru Sato, Atsushi Yamada, Junji Kotani, Tetsuro Ishiguro, Toshihiro Ohki, Shirou Ozaki, Kozo Makiyama, Keiji Watanabe and Kazukiyo Joshin Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi, Kanagawa 243-0197, Japan ABSTRACT In this study, we investigated GaN channel layer quality to suppress drain-lag, which is an important parameter for switching performance. In this experiment, we confirmed that drain-lag performance has dependence on the tilt of the GaN channel layer. GaN channel layer with the tilt angle of 243 arcsec showed faster drain-lag recovery than the tilt angle of 209 arcsec. The results of the drain-lag test and isolation leakage current measurement indicated that the tilt angle and hopping distance contributed to drain-lag recovery. We proposed the mechanism of trap effect during the drain-lag test. INTRODUCTION GaN HEMTs are promising devices for high-voltage switching and a high power amplifier in RF power applications due to their high breakdown voltage and high electron mobility. However, GaN HEMTs performance degradation due to trap effects is well known. A lot of research has been carried out to investigate the origin of traps and the mechanism of device performance degradation caused by these trap effects. The electron trap at Ec - 0.57 eV, which is located in the drain access region is detected by constant drain-current deep level transient spectroscopy [1]. An investigation of trapping phenomena and gate leakage current after a reverse bias stress test was carried out by Rosetto et al [2]. They pointed out that two types of traps lead to leakage current increase and current collapse. Zhou et al. reported that bulk acceptor traps in the GaN buffer layer are important factors of drain current collapse [3]. However, the relationship between channel layer quality and drain-lag has not been fully investigated. In this study, we report on the influence of GaN channel layer quality on drain-lag performance.
EXPERIMENTAL DETAILS We fabricated GaN HEMTs on a SiC substrate with GaN channel layer with different quality (epi-A and epi-B) as shown in Fig. 1. To evaluate the drain-lag
performance, Al-based metal was fabricated as an ohmic electrode and annealed to get ohmic contact. Both samples showed that specific contact-resistance was about 5×10-6cm2. SiN passivation film was deposited on the surface, and an opening was formed for the Schottky contact area by dry etching. The gate electrode was Ni/Au. The gate length (Lg) is 0.5 m and gate periphery (Wg) is 1800 m. To evaluate these crystal quality differences, we measured isolation leakage current. For this measurement, Albased metal was used as an electrode, and between these electrodes, an isolated area was made by Ar+ implantation and isolation gaps were 2, 4 and 6 m to calculate the vertical electric current (I1) of each epitaxial layer. (a)
(b)
Fig. 1. Schematic cross section of devices for measurement; (a) GaN HEMT, (b) Isolated a
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