GaN-on-Silicon CMOS-Compatible Process
To achieve high-volume manufacturing of GaN technology, GaN-on-Si wafers need to be processed in highly efficient and productive CMOS fabs. To achieve this objective, the GaN-on-Si epitaxy and processing technology need to be adapted to the strict standar
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GaN-on-Silicon CMOS-Compatible Process Denis Marcon and Steve Stoffels
3.1
GaN-on-Si Epitaxy
In order to process GaN-on-Si wafers in a CMOS fab, they need to meet the basic criteria for wafer bow. However, due to the large lattice and thermal mismatch between (Al)GaN and Si, growing high-quality crack-free GaN epitaxial layer on 200-mm Si substrates with low bow requires an intensive optimization of the epitaxy [1]. Indeed, the main challenge at the epitaxial level is to obtain a high and uniform epitaxial quality combined with a sufficiently low wafer bow, below 50 µm, to allow processing in a CMOS fab. The wafer bow has been successfully controlled below ±50 µm by using stress-mitigating buffer layers as well as 1.15-mm-thick Si substrates instead of the standard 0.725-mm-thick substrates. An example of stress-mitigating buffer layers is reported in Fig. 3.1. In this case, the buffer consists of a graded AlGaN layer where the Al % is graded from 100 % (AlN nucleation layer) down to 25 % before growing the GaN channel layer (inset Fig. 3.1). Moreover, the buffer layer is engineered in order to reduce the dislocations density in the device active region: in Fig. 3.1 it is possible to notice that most of the dislocations end in the Al(Ga)N buffer layers and only few reach the surface, i.e., the active region. More details on the GaN-on-Si epitaxy can be found elsewhere [1, 2]. The reproducibility of the wafers is also another crucial aspect for high-volume manufacturing of GaN technology. This has been assessed within a lot of identical wafers showing a uniform and reproducible 2DEG sheet resistivity (Fig. 3.2a) as well as a bow below the specification of ±50 µm (Fig. 3.2b), which is the typical maximum allowed bow of wafer to be processed in the CMOS fab.
D. Marcon (&) S. Stoffels IMEC, Leuven, Belgium e-mail: [email protected] © Springer International Publishing Switzerland 2017 M. Meneghini et al. (eds.), Power GaN Devices, Power Electronics and Power Systems, DOI 10.1007/978-3-319-43199-4_3
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Fig. 3.1 TEM image of the full GaN-on-Si epitaxial stack. The upper part, i.e., active region of the stack is magnified in the inset
(a)
20 15 10 5 0 -5 -10 -15 -20 -25 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Average Bow (μm)
(b) 25
Fig. 3.2 Reproducibility within a lot of 18,200-mm GaN-on-Si wafers of the (a) 2DEG sheet resistance and (b) wafer bow
3 GaN-on-Silicon CMOS-Compatible Process
3.2
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GaN-on-Si Au-Free Processing
Conventional III–V processing includes Au-containing metallization schemes patterned by lift-off. Obviously, these metallization schemes are not compatible with a CMOS fab. For this reason, an Au-free process where metals are patterned by dry-etching steps has been developed on standard CMOS tools [3]. Prior to processing, it has been assessed that the thicker and heavier GaN-on-Si wafers could be processed on most production tools without significant hardware or process modifications. Occasionally, the robot speed of the wafer transport systems had to
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