Generic Hardware Architectures for Sampling and Resampling in Particle Filters
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Generic Hardware Architectures for Sampling and Resampling in Particle Filters Akshay Athalye Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY 11794-2350, USA Email: [email protected]
Miodrag Boli´c Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY 11794-2350, USA Email: [email protected]
Sangjin Hong Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY 11794-2350, USA Email: [email protected]
Petar M. Djuri´c Department of Electrical and Computer Engineering, Stony Brook University, Stony Brook, NY 11794-2350, USA Email: [email protected] Received 18 June 2004; Revised 11 April 2005; Recommended for Publication by Markus Rupp Particle filtering is a statistical signal processing methodology that has recently gained popularity in solving several problems in signal processing and communications. Particle filters (PFs) have been shown to outperform traditional filters in important practical scenarios. However their computational complexity and lack of dedicated hardware for real-time processing have adversely affected their use in real-time applications. In this paper, we present generic architectures for the implementation of the most commonly used PF, namely, the sampling importance resampling filter (SIRF). These provide a generic framework for the hardware realization of the SIRF applied to any model. The proposed architectures significantly reduce the memory requirement of the filter in hardware as compared to a straightforward implementation based on the traditional algorithm. We propose two architectures each based on a different resampling mechanism. Further, modifications of these architectures for acceleration of resampling process are presented. We evaluate these schemes based on resource usage and latency. The platform used for the evaluations is the Xilinx Virtex II pro FPGA. The architectures presented here have led to the development of the first hardware (FPGA) prototype for the particle filter applied to the bearings-only tracking problem. Keywords and phrases: particle filters, hardware architectures, memory schemes, real-time processing, bearings-only tracking.
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INTRODUCTION
Particle filters (PFs) [1, 2] are used to perform filtering for models that are described using the dynamic state-space approach [1]. Many problems in signal processing and communications can be described using these models [3]. In most practical scenarios, these models are nonlinear, the states are high-dimensional, and the densities involved are nonGaussian. Traditional filters like the extended Kalman filter (EKF) are known to perform poorly in such scenarios [4]. PFs on the other hand are not affected by the conditions of nonlinearity and non-Gaussianity and handle highdimensional states better than traditional filters [5].
PFs are Bayesian in nature and their goal is to find an approximation to the posterior density of a state of interest (e.g., position of a moving object in tracki
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