Graphene-based photonic synapse for multi wavelength neural networks
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MRS Advances © 2020 Materials Research Society DOI: 10.1557/adv.2020.327
Graphene-based photonic synapse for multi wavelength neural networks Bicky A. Marquez1, Hugh Morison1, Zhimu Guo1, Matthew Filipovich1, Paul R. Prucnal2, and Bhavin J. Shastri1,2 Department of Physics, Engineering Physics and Astronomy, Queen’s University, Kingston, ON K7L 3N6, Canada 1
2
Department of Electrical Engineering, Princeton University, Princeton, NJ 08540, USA
A synapse is a junction between two biological neurons, and the strength, or weight of the synapse, determines the communication strength between the neurons. Building a neuromorphic (i.e. neuron isomorphic) computing architecture, inspired by a biological network or brain, requires many engineered synapses. Furthermore, recent investigation in neuromorphic photonics, i.e. neuromorphic architectures on photonics platforms, have garnered much interest to enable high-bandwidth, low-latency, low-energy applications of neural networks in machine learning and neuromorphic computing. We propose a graphene-based synapse model as a core element to enable large-scale photonic neural networks based on on-chip multiwavelength techniques. This device consists of an electroabsorption modulator embedded in a microring resonator. We also introduce an encoding protocol that allows for the representation of synaptic weights on our photonic device with 15.7 bits of resolution using current control hardware. Recent work has suggested that graphene-based modulators could operate in excess of 100 GHz. Combined with our work, such a graphene-based synapse could enable applications for ultrafast and online learning.
INTRODUCTION The representation of digital information in analog hardware is marking a milestone in the history of information processing. The benefits of analog architectures for accelerating artificial intelligence (AI) applications are considerable. Among these 1
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advantages, we highlight the possibility of designing brain-inspired physical circuits, with which we can solve AI tasks more efficiently. The digital language and the von Neumann architecture have proven inefficient in solving problems that are suited for parallel processing. For example, the training for Google's state-of-the-art large-scale language model BERT (110M parameters) requires 4 days using 16 TPUv2, which corresponds to 12,041.51W and 1,438 lbs of CO2 emissions (equivalent to a trans-American flight) [1]. Such limitations can be overcome through the implementation of photonic analog processing on integrated circuits with small footprint, high-speed and low power consumption [2-7]. A scalable photonic architecture for parallel processing can be achieved by using on-chip wavelength division multiplexed (WDM) techniques [4,8], in conjunction with banks of tunable filters, i.e
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