Modern architecture for photonic networks-on-chip
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Modern architecture for photonic networks‑on‑chip Kapil Sharma1 · Vivek Kumar Sehgal1
© Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Development in photonic integrated circuits (PICs) provides a promising solution for on-chip optical computation and communication. PICs provides the best alternative to traditional networks-on-chip (NoC) circuits which face serious challenges such as bandwidth, latency and power consumption. Integrated optics have substantiated the ability to accomplish low-power communication and low-power data processing at ultra-high speeds. In this work, we propose a new architecture for NoC, which might improve overall on-chip network performance by reducing its power consumption, providing large channel capacity for communication, decreasing latency among nodes and reducing hop count. Some of the key features of the proposed architecture are to reduce the waveguide network for communication among nodes, and this architecture can be used as a brick to construct other architectures. In this architecture, we use micro-ring resonator (MRR) and it is used to provide a high bandwidth connection among nodes with a lesser number of waveguide networks. Furthermore, results show that this architecture of PICs provides better performance in terms of low communication latency, low power consumption, high bandwidth. It also provides acceptable FSR value, FWHR value, finesse value and Q-factor of micro-ring resonators used for the design of MRR in this architecture. Keywords Photonic integrated circuits · Micro-ring resonator · Networks-on-chip
1 Introduction NoC is a concept to integrate different IP cores on a single chip in a network topology [1]. Its main purpose is to combine all elements like RAM, ROM, computing processors, sensors in the form of MEMS, GPU and other operating units on a * Vivek Kumar Sehgal [email protected] Kapil Sharma [email protected] 1
Department of Computer Science and Engineering, Jaypee University of Information Technology, Waknaghat, Solan, H.P., India
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single chip. These connections between elements play a major role in communication among them. It consists of specific routers that act as a medium to route packets between destination and source. These routers act as per the routing algorithm and topology used in NoC to decide further hops [2]. Some of the main features of network-on-chip are: (a) scalability: to use all elements efficiently and reduce system size, (b) power efficiency: to enhance overall communication on a single chip which reduces power consumption, (c) reduced latency: to make dedication connection between elements which reduces high communication latency and (d) predictability: As connection among devices is well controlled and optimized under electrical parameters, we can predict NoCs throughput in terms of power consumption as well as transmission delay. To understand the importance of NoC, it is important to consider past challenges [2]. Let us look in the past
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