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Recently, various two-dimensional (2D) materials, such as graphene, transition metal dichalcogenides and so on, have attracted much attention in electron device research. The most important characteristic of graphene is its highest mobility of all semiconductor channels at room temperature. However, it is obvious that more than a good mobility characteristic is required to realize the field effect transistor (FET), and intense arguments from various points of view are necessary. In this paper, the issues with Si-metal oxide semiconductor FETs (Si-MOSFET) and the advantage of 2D materials are discussed. The present state of graphene FETs with respect to gate stack formation and band gap engineering is reported. Moreover, based on the density of states (DOS) of graphene extracted using the quantum capacitance (CQ) measurement, it is shown that the electric band structure of graphene in contact with gate insulators or metal electrode deviates from its intrinsic band structure. Kosuke Nagashio received the BE degree in Materials Science & Engineering from Kyoto University in 1997 and the ME and PhD degrees in Materials Engineering from The University of Tokyo in 1999 and 2002, respectively. He is currently an Associate Professor with the Department of Materials Engineering, The University of Tokyo. His research interests presently focus on the carrier transport for layered materials and the crystal growth. Dr Nagashio is a member of the Japan Society of Applied Physics (JSAP), the Japan Institute of Metals (JIM), the Materials Research Society (MRS) and the IEEE Electron Device Society (EDS).

Kosuke Nagashio

I. ISSUES WITH Si-MOSFET AND THE ADVANTAGE OF 2D CHANNELS

The issues with the miniaturization of Si-MOSFETs are generically called short channel effects.1 When the source and drain depletion regions become comparable in length with the channel length, as shown in Fig. 1(a), the drain bias weakens the gate bias, which leads to a drastic increase in the off-current. Based on an analysis of the distribution of the electrical potential in the channel region, it is widely known that the short channel effect can be neglected when the channel length is ;6 times ffi longer than the scaling length, pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi k ¼ ðech tch tox Þ=ðNeox Þ,2,3 where ech, eox, tch, and tox are the dielectric constants for the channel, the gate insulator, the thickness of the channel, and the gate oxide,

Contributing Editor: Mauricio Terrones a) Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/jmr.2016.366

respectively. Figure 1(b) shows the 6k values calculated for Si, carbon nanotubes (CNT), bilayer graphene, and MoS2, where the contribution of the tunneling effect is neglected. N is defined as the effective gate number: N 5 1 for planar, N 5 2 for dual gate, N 5 3 for FIN-FET, and N 5 4 for gate-all-around. Although the FIN structure has already been adopted for Si to reduce the short channel effects,4 it is difficult to avoid the short channel effects for channel lengths