Nanowire Tunnel FETs - Device Structure, Transistor Dimension and Material Choice
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Nanowire Tunnel FETs - Device Structure, Transistor Dimension and Material Choice J. Knoch1 1 TU Dortmund University, 44227 Dortmund, Germany ABSTRACT The performance of tunnel FETs is investigated and the impact of device structure and dimension as well as the impact of the transistor material will be studied. For instance, using nanowires with thin diameter providing one-dimensional transport together with a wrap-gate device structure strongly improves the tunnel FET performance. In addition, the use of III-V type II heterostructures is a further performance booster. However, the use of III-V semiconductors with low density of states can be problematic if the device is not designed properly. Here we will give design guidelines and performance predictions of nanowire tunnel FETs based on nonequilibrium Greens functions formalism simulations. INTRODUCTION The power consumption of integrated circuits has recently become one of the major issues limiting a further increase of clock speed and integration density. The reason for this is the fact that conventional field-effect transistors (FETs) exhibit a minimum inverse subthreshold slope of 60mV/dec irrespective of dimensionality, material in use or transistor dimensions. The minimum inverse subthreshold slope in turn sets a lower limit for the supply voltage Vdd of integrated circuits of approximately 1V. Scaling Vdd below this limit yields either a drastically reduced performance or unacceptably high leakage currents. Tunnel FETs (TFETs) have recently attracted a great deal of interest since they potentially allow realizing an inverse subthreshold slope steeper than 60mV/dec due to field-effect controlled band-to-band tunneling (BTBT). As a result, TFETs hold promise to significantly lower the power consumption due to very small offstate leakage currents yielding a reduced static power as well as a decrease in supply voltage and thus in dynamic power Pdyn since Pdyn ∝ Vdd2 . However, to date, the best performing experimental TFETs still exhibit a poor on-state and a subthreshold swing S
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