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36

GaAs wafers up to 4 inches in diameter, with electrical properties homogenized by whole ingot annealing, are currently available from U.S. domestic and overseas suppliers. However, the Overall quality is compromised by the large dislocation densities, varying 104 - 105/ cm2. This density ränge is characteristic of the LEC process. To be sure, a unanimity of views is lacking among device technologists whether dislocation-free Substrates are essential to attain Performance objectives in high speed circuits based on majority carrier injection principles. It is, however, likely that with the advent of large-scale integration the need for low dislocation density material will become ine vi table. This view is supported by the work of Hirayama et al.,10 who reported on the fabrication of 16 kbit stark RAMs comprising more than 105 FETs using In-alloyed "nearly dislocation-free" (1.27 x 10'6cm-3, and O represents 5.7 x 1015cm~3, and O represents 1.41 x 10'6cnr3, and D represents