Growth of 3C-SiC Layers on Silicon Substrates with a Novel Stress Relaxation Structure
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Growth of 3C-SiC Layers on Silicon Substrates with a Novel Stress Relaxation Structure Yoshihiro Irokawa, Noboru Yamada, Masahito Kodama, and Tetsu Kachi Toyota Central Research & Development Laboratories, Inc., Nagakute, Aichi, 480-1192, JAPAN ABSTRACT Silicon (Si) substrates having cavities just beneath the surface layer (multi-cavity Si substrates) were examined whether they worked as the stress relaxation structure in 3C-SiC heteroepitaxial growth on Si. Single crystalline 3C-SiC layers were grown on the multi-cavity Si substrates by means of low pressure chemical vapor deposition (LPCVD). The layers’ quality was characterized by the cross-sectional TEM observations and the Micro-Raman spectroscopy. The TEM results showed that this structure reduced the defect density in the 3C-SiC layers. The averaged full width at half-maximum (FWHM) of LO Raman mode in the 3C-SiC layers on the multi-cavity Si substrates became narrower than that on the conventional Si substrates. Furthermore, Schottky barrier structures showed that the reverse leakage current of the diodes using the multi-cavity Si substrates is smaller than that using the conventional Si substrates. These results indicate that the multi-cavity Si substrates are effective for stress relaxation in the 3C-SiC layers. INTRODUCTION Silicon carbide (SiC) has long been of interest for potential technological application, such as power devices and sensors, as one of the wide band gap semiconductors. It is a polytype material. The 4H and 6H type SiC wafers are supplied commercially. However, their high cost and the difficulty in obtaining large area are problems for their commercial use. One way to overcome these problems is to use heteroepitaxially grown 3C-SiC layers on Si substrates. The use of Si substrates may make it possible to obtain larger area SiC at low cost and realize the combined devices of Si and SiC. Furthermore, the 3C-SiC polytype of SiC is particularly desirable for its high electron mobility compared to the 6H polytype. Because of a 20% mismatch in the lattice constants of Si and 3C-SiC and an 8 % mismatch in the thermal expansion coefficient, however, the resulting 3C-SiC films were not of device grade quality. The ideal substrates to overcome these mismatches are the thin freestanding substrates [1]. Twist-bonded Universal Compliant (UC) substrates are examples to realize the ideal substrates [2]. However, it is difficult to make the large freestanding UC substrates. As one example of the approximate ideal substrates, silicon on insulator (SOI) substrates were used [3,4]. The thin Si E3.11.1
layers on the buried SiO2 layers were expected to act as compliant layers and relax the stress. , however, there is a Because the general growth temperature of 3C-SiC is over 1300 reservation that the buried SiO2 layers are damaged [4]. Furthermore, the vertical devices can’t be made of the SOI substrates due to the buried SiO2 layers. As another example of approximate ideal substrates, porous Si substrates were proved to be excellent compliant substrates
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