Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications
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RESEARCH ARTICLE-ELECTRICAL ENGINEERING
Heuristic Analysis of CIC Filter Design for Next-Generation Wireless Applications A. Abinaya1 · M. Maheswari1 · Abdullah Saleh Alqahtani2 Received: 9 June 2020 / Accepted: 4 October 2020 © King Fahd University of Petroleum & Minerals 2020
Abstract This paper describes a novel multistage CIC filter which plays a vital role in software-defined radio (SDR) applications. In order to operate the baseband signal, wireless networking standards demand different sample rates. As a result, sample rate conversion (SRC) turns out as a pivotal method of SDR. Thus, cascaded integrator comb (CIC) filter is a distinct kind of linearphase FIR filter which can be used as a decimation filter for SRC operation. The architecture of this filter is multiplierless with low passband droop; hence, it requires less area in contrast to other decimation filters. In this brief, the fundamental structure of CIC filter is examined with various parallel prefix adders and also the significant parameters of the CIC filter for different adders are exemplified. The proposed CIC filter with various parallel prefix adders has been designed in Verilog HDL using Xilinx ISE 14.7 and implemented on Kintex7 FPGA. The schemed CIC filter design is compared with the traditional CIC filter in view of area, speed and power consumption. Based on the obtained results on Kintex7 FPGA, the CIC filter with Brent Kung adder outperforms in terms of LUTs by 41.67% and power by 34.78% compared with the classical CIC filter and among the CIC filters using other parallel prefix adders. The proposed CIC uses new polynomial method which provides 33.33% reduction in passband droop and 41.14% reduction in stopband ripple compared to the existing sharpened CIC. Keywords Software-defined radio · Sample rate · Decimation · Parallel prefix adder · Verilog HDL
1 Introduction The software-defined radio (SDR) plays a crucial role in a recent communication field somewhere all the signal processing is done in the form of digital [1]. The RF signal received from ADC must be translated to desire sample rates essential for signal processing for different air interfaces. The most promising ADCs are implemented using upsam pling and then sigma-delta ( )modulation process along with decimation [2]. Upsampled modulator offers more
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A. Abinaya [email protected] M. Maheswari [email protected] Abdullah Saleh Alqahtani [email protected]
1
Department of Electronics and Communication Engineering, K. Ramakrishnan College of Engineering, Tiruchirappalli, India
2
Department of Computer Science and Self-Development Skills, CFY Deanship, King Saud University, Riyadh, Saudi Arabia
tenacious sampled output nevertheless to the typical Nyquist sampling method. Regardless of the output, the SRC operation is required for the purpose of dropping the sampling frequency and attaining optimum results. Henceforth, the CIC filter design is a recommended method for SRC operation. The CIC filters are pellucid multiplierless decimation filter used for sampl
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