High-flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor
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ORIGINAL RESEARCH
High‑flexible hardware and instruction of composite Galois field multiplication targeted at symmetric crypto processor Yang Su1,2 · Bai‑Long Yang1 · Chen Yang3 · Jing‑Yuan He1,4 Received: 11 December 2019 / Accepted: 27 August 2020 © Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract Composite Galois field multiplication is one of the most important and complex nonlinear arithmetic unit in symmetric cipher algorithms. However, current hardware implementations are hard to maintain high performance and flexibility. Based on reconfigurable technology, we propose a flexible architecture of composite Galois field multiplication (RCGFM) and dedicated instructions of composite Galois filed multiplication (ICGFM) over GF((2n )m ) , where n = 8, m = 1, 2, 3, 4 . The RCGFM adopts a serial–parallel mixed structure, which can achieve different Galois field multiplications with good parallelism and scalability. By extending the xk B multiplications of serial chain, where k = 1, 2, 3 , the RCGFM can concurrently support the composite Galois filed multiplications with higher orders, such as GF((28 )m ) , where m ≥ 5, m ∈ ℤ+ . Moreover, in order to reduce the instruction overhead of target symmetric crypto processor, the ICGFM is specially designed, which is composed of operation and configuration instructions for xk B and A × B over GF((2n )m ) . The ICGFM can be applied to RCGFM structure efficiently and flexibly by configuring the corresponding parameters. The experimental results show that under 0.18 µm CMOS technology, the maximum clock frequency is 625 MHz, while the area of circuit is 11.2 kilo gates. Compared with current researches, the RCGFM structure can improve the throughput rate more than a factor of 1.36x–9.19x, when normalized to the same technology and per kilo gates, the technology-scaled throughput rate increases more than a factor of 1.25x–4.4x, while the area overhead does not increase significantly. In addition, the ICGFM can reduce 1–2 orders of magnitude the number of instructions compared with other works. At last, the reconfigurable architecture we proposed supports different composite Galois field multiplications over GF((2n )m ) with more flexibility and efficiency. Keywords Composite Galois field multiplication · Reconfigurable hardware · Flexible structure · Dedicated instruction · Symmetric crypto processor
1 Introduction With rapid development of cloud computing, Internet of Things (IoT) (Mario et al. 2018), Artificial Intelligence (AI) (Basallo et al. 2018), Wireless Sensor Networks (WSN) (Xie
et al. 2019) and other emerging technologies, the security of data transmission and storage is becoming more and more important. As the main means of providing confidentiality services, symmetric cryptography has been used to construct pseudo-random number generator, stream cipher, the core 2
* Chen Yang [email protected]
School of Cryptography Engineering, Engineering University of PAP, No. 1 Wujing Road, WeiYang District, Xi’an 710086, China
3
Bai‑Long
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