High-k ZrO 2 Gate Dielectric on Strained-Si
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HIGH-k ZrO2 GATE DIELECTRIC ON STRAINED-Si S. Bhattacharya1*, S. K. Samanta2, S. Chatterjee2, John McCarthy3, B. M. Armstrong1, H. S. Gamble1, C. K. Maiti2, T. Perova3 and A. Moore3 1
School of Electrical & Electronic Engineering, The Queen's University of Belfast, United Kingdom 2 Department of Electronics & ECE, Indian Institute of Technology, Kharagpur 721302, India 3 Department of Electrical & Electronic Engineering, Trinity College, University of Dublin, Ireland E-mail: [email protected] Fax: 44 2890 667023 ABSTRACT The growth and structural characterization of UHV-compatible LPCVD grown strained-Si layer on linearly graded relaxed SiGe layer and the electrical properties of the high-k ultrathin ZrO2 films deposited on strained-Si layer using microwave-plasma CVD at low temperature (150oC) are reported. The strained-Si layer has been characterized using AFM, TEM and Raman spectroscopy. The C-V and G-V characteristics of ZrO2 films have been used to calculate the interface trap density, Dit, near the midgap energy, and the fixed oxide charge density, Qf/q. These are found to be 2.24 x 1012 cm-2 eV-1 and 1.45 x 1011 cm-2, respectively. Poole-Frenkel (PF) conduction mechanism is found to dominate the current conduction at room temperature. INTRODUCTION Fundamental limits to CMOS scaling are rapidly approaching as devices are scaled below the 50 nm ranges. New methods and materials for CMOS fabrication must be investigated to allow continued device improvement. According to the Semiconductor Industry Association (SIA) roadmap, 15 Å gate oxides will be needed for the sub-100 nm technology node in 2005 [1]. However, the use of conventional SiO2 is not possible, as it shows a high leakage current of the order of 1 A/cm2 at a 2.0 V gate bias. Gate leakage reduction in ultrathin gate dielectrics is the main motivation for the search of high-k materials. As a result, alternative gate insulators with higher dielectric constant than SiO2 such as Ta2O5, ZrO2, Al2O3, Y2O3, (Ba, Sr)TiO3, Pb(Zr, Ti)O3, Nb2O5, HfO2 and TiO2 are currently being investigated for future generation MOS devices. ZrO2 is being considered as a potential candidate for the replacement of SiO2 due to its high dielectric constant (15–22), wide band gap (4.6–7.8 eV), high breakdown field (15–20 MV cm-1) and superior thermal stability [2, 3]. Recently, the use of biaxial strained-Si has attracted considerable attention for advanced CMOS devices because of enhancements of in-plane mobility of both the electrons and holes compared to bulk-Si [4, 5]. Compared to the alternatives, strained-Si surface channel MOSFETs have the following additional advantages: the surface channel architecture leads to better scaling behavior
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in deep submicron channel lengths, and advanced gate oxides can be thermally grown on pure Si as opposed to SiGe. In this paper, we present the results of our study on the growth and structural characterization of UHV-compatible LPCVD grown strained-Si films on linearly graded relaxed SiGe layer. The strained-Si has been ch
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