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D4.1.1

Investigations of Metal Gate Electrodes on HfO2 Gate Dielectrics Jamie Schaeffer, Sri Samavedam, Leonardo Fonseca, Cristiano Capasso, Olubunmi Adetutu, David Gilmer, Chris Hobbs, Eric Luckowski, Rich Gregory, Zhi-Xiong Jiang, Yong Liang, Karen Moore, Darrell Roan, Bich-Yen Nguyen, Phil Tobin, Bruce White Motorola, Inc., Advanced Products Research and Development Laboratory Austin, TX 78721

ABSTRACT As traditional poly-silicon gated MOSFET devices scale, the additional series capacitance due to poly-silicon depletion becomes an increasingly large fraction of the total gate capacitance, excessive boron penetration causes threshold voltage shifts, and the gate resistance is elevated. To solve these problems and continue aggressive device scaling we are studying metal electrodes with suitable work-functions and sufficient physical and electrical stability. Our studies of metal gates on HfO2 indicate that excessive inter-diffusion, inadequate phase stability, and interfacial reactions are mechanisms of failure at source drain activation temperatures that must be considered during the electrode selection process. Understanding the physical properties of the metal gate - HfO2 interface is critical to understanding the electrical behavior of MOS devices. Of particular interest is Fermi level pinning, a phenomenon that occurs at metal – dielectric interfaces which causes undesirable shifts in the effective metal work function. The magnitude of Fermi level pinning on HfO2 electrodes is studied with Pt and LaB6 electrodes. In addition, the intrinsic and extrinsic contributions to Fermi level pinning of platinum electrodes on HfO2 gate dielectrics are investigated by examining the impact of oxygen and forming gas anneals on the work function of platinum-HfO2-silicon capacitors. The presence of interfacial oxygen vacancies or Pt-Hf bonds is believed to be responsible for a degree of pinning that is stronger than predicted from the MIGS model alone. Interface chemistry and defects influence the effective metal work function.

INTRODUCTION Since increasing the gate capacitance is required for increasing MOSFET drive current, device scaling mandates an elimination of additional factors contributing to the inversion capacitance (Cinv). When a MOSFET is operated in inversion there are actually two additional capacitances in series with the oxide capacitance. Taking these factors into consideration the total capacitance is given by 1/Cinv = 1/Csub + 1/Ci + 1/Cpoly where Ci is the aforementioned oxide capacitance, Csub is a capacitance due to quantum mechanical effects which force the centroid of inversion charge in the substrate to be a few Ångstroms away from the Si/SiO2 interface, and Cpoly is a capacitance due to a gradual potential drop, or band bending, in the poly-Si gate electrode. The Cpoly contribution, which is referred to as poly-silicon (poly-Si) depletion, is a result of the sum of inversion and depletion charges in the substrate being greater than the doping density (Npoly) near the poly-Si - oxide interface. Si