High quality and high speed cutting of 4H-SiC JFET wafers including PCM structures by using Thermal Laser Separation
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High quality and high speed cutting of 4H-SiC JFET wafers including PCM structures by using Thermal Laser Separation Dirk Lewke1, Matthias Koitzsch1, Karl Otto Dohnke2, Martin Schellenberger1, Hans-Ulrich Zuehlke3, Roland Rupp2, Lothar Pfitzner1, and Heiner Ryssel1 1 Fraunhofer Institute for Integrated Systems and Device Technology IISB; Erlangen, Germany. 2 Infineon Technologies AG; Erlangen, Germany 3 3D-Micromac AG; Chemnitz, Germany
ABSTRACT The silicon carbide (SiC) market is gaining momentum hence productivity in device manufacturing has to be improved. The current transition from 100 mm SiC-wafers to 150 mm SiC-wafers requires novel processes in the front-end as well as the back-end of SiC-chip production. Dicing of fully processed SiC-wafers is becoming a bottleneck process since current state-of-the-art mechanical blade dicing faces heavy tool wear and achieves low throughput due to low feed rates in the range of only a few mm/s. This paper presents latest results of the novel dicing technology Thermal Laser Separation (TLS) applied for separating SiC-JFETs. We demonstrate for the first time that TLS is capable of dicing fully processed 4H-SiC wafers, including back side metal layer stacks, process control monitoring (PCM), and metal structures inside the dicing streets with feed rates up to 200 mm/s. TLS thus paves the way to efficient dicing of 150 mm SiC-wafers. INTRODUCTION With the ramp-up of 150 mm SiC wafer capacity, SiC is projected to become a part of mass manufacturing in the semiconductor industry within the next ten years [1]. The major sectors currently driving the demand for SiC-based electron devices are inverters for photovoltaic, power factor correctors [2] and automotive applications, i.e., power electronics for electric vehicles and hybrid electric vehicles. With the transition from 100 mm SiC-wafers to 150 mm SiC-wafers, one important challenge has to be met: Dicing of fully processed wafers at high speed without damaging the chips. This paper presents and discusses latest results of Thermal Laser Separation applied for dicing fully processed 4H-SiC-based JFET wafers. Special focus was put on separating wafers with structures inside the dicing street, i.e., process control monitoring and metal structures. Light microscopy and scanning electron microscopy was used to investigate the resulting edge quality. Finally, TLS-cut SiC-JFETs were characterized with regard to their electric behavior. STATE-OF-THE-ART Well-known mechanical blade dicing is currently used for separating SiC-based electron devices [3]. In this case, a fast rotating blade with fine diamond abrasives is guided along each dicing street of a wafer. Due to the hardness of SiC – 9.2 on Mohs scale [4] – SiC-wafers can only be diced at low feed rates in a range of a few mm/s using mechanical blade dicing. Besides the low feed rate, dicing blades face high tool wear increasing the danger of uncontrolled tool
breakage during dicing. Uncontrolled tool breakage decreases yield and increases overall process time because of the n
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