High Rate Silicon Carbide Polishing to Ultra-Smooth Surfaces
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0991-C07-02
High Rate Silicon Carbide Polishing to Ultra-Smooth Surfaces Michael L. White, Kevin Moeggenborg, Francois Batllo, Jeffrey Gilliland, and Nevin Naguib Cabot Microelectronics, Aurora, IL, 60504
Abstract Silicon Carbide has a unique combination of properties that include a nearly diamond-like hardness, intrinsic electrical semiconductivity and a high thermal conductivity.1 This combination of properties has led to itís use in a number of applications including substrates for Light Emitting Diodes (LEDs), power, RF (radio frequency) and other electronic devices in addition to mirror substrates and optical devices as well as stop layers in integrated circuit chip manufacture. In addition, the chemical inertness and high hardness of SiC has historically resulted in low removal rates during chemical mechanical Planarization (CMP). Recent efforts in our labs have led to being able to polish single crystal silicon carbide at removal rates up to 400 nm/hr yielding a root mean squared roughness on the order of a nanometer as determined by AFM and interferometry. The high rates and smoothness obtained are expected to translate to other types of silicon carbide. Fundamental studies by FTIR, streaming potential and ESCA have been done to elucidate the mechanism of silicon carbide polishing.
Introduction Recently, there has been a great deal of interest in polishing single crystal silicon carbide. Silicon carbide has over 200 different allotropic forms, including various polytypes.1 However, 4H and 6H SiC are used for the majority of electronic applications including as substrates for LEDs, RF and power devices. In addition, various orientations relative to the c-axis exist with 0o, 4o and 8o off-cut angles being the most common and various dopants and doping levels are prevalent depending upon the specific application.1,2 It is necessary to polish single crystal silicon carbide to remove subsurface damage (SSD) caused by cutting operations with a wire saw. A traditional route would involve lapping or polishing with one or more grades of diamond followed by CMP with high pH, colloidal silica based slurries.2 However, these routes yield very low removal rates on single crystal silicon carbide. Rates lower than 20 nm/hr seem to be typical.2,3 Several critical factors must ultimately be considered when developing appropriate CMP slurry formulations to polish single crystal silicon carbide. These include removal rate and surface roughness as well as defect generation including scratches and subsurface damage created by the polishing process if conditions such as the down force or table speed are not properly controlled. The elimination of these
defects is important for obtaining high manufacturing yields and for devices prepared on polished single crystal silicon carbide to display optimal electrical performance. For instance, the elimination of SSD is a critical factor in LED brightness.4 This paper will focus on the challenges associated with achieving high removal rates on n-doped, single crystal, 4o off-axis, 4HN
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