High-temperature in situ cross-sectional transmission electron microscopy investigation of crystallization process of yt
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Naoki Wakiya and Kazuo Shinozaki Department of Metallurgy and Ceramics Science, Tokyo Institute of Technology, Meguro-ku, Tokyo 152-8552, Japan
Nobuyasu Mizutani Center for Advanced Materials Analysis, Tokyo Institute of Technology, Meguro-ku, Tokyo 152-8550, Japan; and Department of Metallurgy and Ceramics Science, Tokyo Institute of Technology, Meguro-ku, Tokyo 152-8552, Japan (Received 19 November 2004; accepted 25 March 2005)
The crystallization process of yttria-stabilized zirconia (YSZ) gate dielectrics deposited on p-Si (001) and SiOx /p-Si(001) substrates and the growth process of SiOx has been investigated directly using high-temperature in situ cross-sectional view transmission electron microscopy (TEM) method and high-temperature plan-view in-situ TEM method. The YSZ layer is crystallized by the nucleation and growth mechanism at temperatures greater than 573 K. Nucleation originates from the film surface. Nucleation occurs randomly in the YSZ layer. Subsequently, the crystallized YSZ area strains the Si surface. Finally, it grows in the in-plane direction with the strain, whereas, if a SiOx layer of 1.4 nm exists, it absorbs the crystallization strain. Thereby, an ultrathin SiOx layer can relax the strain generated in the Si substrate in thin film crystallization process.
I. INTRODUCTION
Yttria-stabilized zirconia (YSZ) thin film is widely used as a gate dielectric and a buffer layer for oxide electronics device such as ferroelectric gate transistor.1–7 It has several excellent properties: a relatively highdielectric constant (∼25, so-called high-K material), an interdiffusion barrier, low-leakage current, a wide band gap (∼5.6 eV), an adequate band offset with Si (1.4 eV), thermal and chemical stability, epitaxial growth on a Si substrate, and others. In particular, these devices use only the surface region of a silicon wafer less than 10 nm as a gate channel, which is a carrier path in the metalinsulator-semiconductor (MIS) structure. Then the interface structure and properties control MIS-type device performance. On the other hand, YSZ/Si interface is an oxide/Si heterojunction; for that reason, the SiOx layer should be considered. Therefore, it is necessary to consider the effect of a SiOx layer on YSZ film growth and a)
Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/JMR.2005.0234 1878
http://journals.cambridge.org
J. Mater. Res., Vol. 20, No. 7, Jul 2005 Downloaded: 05 Apr 2015
interface formation. For this purpose, the in situ transmission electron microscopy (TEM) method presents great advantages because of its nanometer scale spatial resolution and real-time imaging.8–11 Several groups have already conducted in situ film deposition experiments in a TEM specimen chamber.8–11 However, the materials are restricted to metal or semiconductor that evaporate easily at low temperatures by vacuum evaporation or molecular beam epitaxy (MBE) method combined with (ultrahigh vacuum) TEM instruments. As a technical issue, many oxide materials including YSZ h
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