Highly Flexible Multimode Digital Signal Processing Systems Using Adaptable Components and Controllers
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Highly Flexible Multimode Digital Signal Processing Systems Using Adaptable Components and Controllers Vinu Vijay Kumar and John Lach Charles L. Brown Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA Received 1 October 2004; Revised 21 March 2005; Accepted 25 May 2005 Multimode systems have emerged as an area- and power-efficient platform for implementing multiple timewise mutually exclusive digital signal processing (DSP) applications in a single hardware space. This paper presents a design methodology for integrating flexible components and controllers into primarily fixed logic multimode DSP systems, thereby increasing their overall efficiency and implementation capabilities. The components are built using a technique called small-scale reconfigurability (SSR) that provides the necessary flexibility for both intermode and intramode reconfigurabilities, without the penalties associated with general-purpose reconfigurable logic. Using this methodology, area and power consumption are reduced beyond what is provided by current multimode systems, without sacrificing performance. The results show an average of 7% reduction in datapath component area, 26% reduction in register area, 36% reduction in interconnect MUX cost, and 68% reduction in the number of controller signals, with an average 38% increase in component utilization for a set of benchmark 32-bit DSP applications. Copyright © 2006 Hindawi Publishing Corporation. All rights reserved.
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INTRODUCTION
The burgeoning demand for high performance DSP systems has spurred widespread research on efficient platforms for implementing arithmetic intensive applications characteristic of such systems. Based on these applications’ high throughput requirements, fixed logic application-specific integrated circuits (ASICs) are normally the platform of choice. However, their lack of flexibility is disadvantageous in today’s world of disparate and rapidly evolving standards and applications, which require the execution of a variety of DSP tasks. In the absence of flexibility, direct hardware implementation of all of the tasks is the only option and can be prohibitively expensive—even in this “transistors for free” era. This has led to the search for new methods for adding flexibility to otherwise fixed logic DSP circuits, without having to pay the large performance, area, and power penalties associated with field programmable gate arrays (FPGAs), DSP processors, or even application-specific instruction processors (ASIPs). An emerging platform that has been proposed to address the flexibility issue in ASICs for DSP is “multimode” systems [1, 2]. Tasks that are timewise mutually exclusive are synthesized to the same hardware area, allowing the tasks to be separated temporally rather than spatially. When a particular task must be executed, the system switches to the appropriate hardware configuration “mode.” Such a design platform can prove useful for many DSP systems. For example,
a system jointly implementing two different sta
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