Improvement of Minority Carrier Lifetime in Thick 4H-SiC Epi-layers by Multiple Thermal Oxidations and Anneals
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Improvement of Minority Carrier Lifetime in Thick 4H-SiC Epi-layers by Multiple Thermal Oxidations and Anneals Lin Cheng1, Michael J. O'Loughlin1, Alexander V. Suvorov1, Edward R. Van Brunt1, Albert A. Burk1, Anant K. Agarwal1, and John W. Palmour1 1 Cree, Inc. 4600 Silicon Drive, Durham, NC 27703 ABSTRACT This paper details the development of a technique to improve the minority carrier lifetime of 4HSiC thick (≥ 100 μm) n-type epitaxial layers through multiple thermal oxidations. A steady improvement in lifetime is seen with each oxidation step, improving from a starting ambipolar carrier lifetime of 1.09 μs to 11.2 μs after 4 oxidation steps and a high-temperature anneal. This multiple-oxidation lifetime enhancement technique is compared to a single high-temperature oxidation step, and a carbon implantation followed by a high-temperature anneal, which are traditional ways to achieve high ambipolar lifetime in 4H-SiC n-type epilayers. The multiple oxidation treatment resulted in a high minimum carrier lifetime of 6 μs, compared to < 2 μs for other treatments. The implications of lifetime enhancement to high-voltage/high-current 4H-SiC power devices are also discussed. INTRODUCTION The quality of thick 4H-SiC n-type epitaxial layers has increased dramatically in recent years. 4 inch wafers with blocking layers thicker than 100 μm and doping concentrations of less than 2x1014 cm-3 can now be readily fabricated, making bipolar 4H-SiC power devices such as GTOs and PiN diodes a viable prospect for pulse power applications with voltage ratings of 10 kV and beyond [1]. In addition to supporting high voltage, these devices must also operate at high current densities. A key factor to achieve good on-state performance is a high ambipolar carrier lifetime in the device's drift region. This effect becomes more important for thicker epitaxial regions when aiming for much higher blocking voltages. For devices with ≥ 100 μm thick as-grown drift regions, typically observed lifetimes are in the range of 1 μs and insufficient to achieve full conductivity modulation in the drift region at high current density, leading to high on-state voltages and high conduction losses [1]. Several techniques to enhance the ambipolar lifetime beyond values present after crystal growth have been developed following the identification of an electron trap (Z1/2) as the main lifetime killer in 4H-SiC epitaxial layers [2]. Growing epitaxy in a carbon-rich environment had been shown to provide higher ambipolar lifetime, but at the cost of a greater density of epitaxial defects [2]. Consequently, post-epitaxial growth lifetime enhancement techniques that involved the annihilation of the carbon vacancies with carbon interstitials were developed, with the interstitials either released through thermal oxidation [3] or introduced by carbon implantation [2]. This work examines the effects of repeated thermal oxidation cycles on the ambipolar lifetime of thick (≥ 100 μm) 4H-SiC epitaxial layers. A series of 5 hour 1300ºC oxidation cycles were performed, followe
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