In-Situ Characterizarion of Interfaces-Induced Resistivity in Nanometric Dimensions
- PDF / 291,352 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 74 Downloads / 193 Views
0914-F06-03
In-Situ Characterizarion of Interfaces-Induced Resistivity in Nanometric Dimensions Hagay Marom, and Moshe Eizenberg Materials Engineering, Technion – Israel Institute of Technology, Technion City, Haifa, Israel
ABSTRACT To improve the speed of integrated circuits it is highly important to minimize the electrical resistivity of their interconnects. However, as the dimensions of the interconnects approach the mean free path of the electrons, a substantial rise in resistivity occurs due to additional electron scatterings from grain boundaries and interfaces. To investigate the role of interfaces, in-situ resistivity measurements were preformed for thin copper films on which different materials were deposited. The resistivity was monitored before and after the deposition, enabling to observe the changes as a new top interface was created. Among the materials tested, tantalum resulted in the highest resistivity increase. This fact is of special importance since this material and its nitride serve today as the common diffusion barrier for copper metallization. Titanium resulted in a smaller resistivity increase, but still higher than that of a free copper surface in vacuum. The developed approach enables to test the influence of different diffusion barriers on copper resistivity. With the continuously shrinking dimensions of copper interconnects, this factor will have an increasing importance in future technology nodes. INTRODUCTION In comparison to bulk materials, the electrical resistivity in nanometric dimensions is influenced by two main additional factors – interfaces and grain boundaries. These factors serve as additional scattering centers for the conduction electrons, causing the resistivity to increase when dimensions approach the mean free path of the electrons. Only then collisions of the electrons with the interfaces and grain boundaries have a substantial contribution in comparison to the collisions with other lattice imperfections. This phenomenon has special importance for the microelectronic industry since the main speed limitation of integrated circuits today derives from the delay time of the electrical signals passing through these interconnects. When the dimensions of interconnects approach the mean free path of the electrons (~40 nm for copper at room temperature), a substantial increase in resistivity is observed [1,2] with harmful influence on speed and performance. This issue has recently been acknowledged by the ITRS (International Technology Roadmap for Semiconductors) as one of the most important obstacles (and challenges) for the future of the microelectronic industry [3]. In previous studies we investigated the roles of grain boundaries [4] and of surface roughness [5] in increasing the resistivity of nanometric copper structures. In this study we focus on the role of interfaces and try to understand whether they can alter the resistivity values. For that purpose a special tool was developed that enables in-situ resistivity measurements inside a deposition chamber. Unlike previo
Data Loading...
