In situ stress measurements during direct MOCVD growth of GaN on SiC
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Joan M. Redwinga),b) Department of Materials Science and Engineering, The Pennsylvania State University, University Park, Pennsylvania 16802, USA; and Materials Research Institute, The Pennsylvania State University, University Park, Pennsylvania 16802, USA (Received 17 April 2015; accepted 30 June 2015)
In situ curvature measurements were used to compare the stress evolution of GaN films grown directly on 6H-SiC via a two-step temperature growth to films grown with an AlN buffer layer. The two-step temperature growth consisted of an initial low-temperature and a main high-temperature GaN layer. In the case of GaN grown directly on 6H-SiC, the high-temperature layer initiated growth under compressive stress which transitioned to tensile stress. Films grown directly on 6H-SiC exhibited a reduction in the threading dislocation (TD) density and an improvement in the surface roughness compared to growth on the AlN buffer layer. Furthermore, transmission electron microscopy of the GaN grown directly on 6H-SiC revealed predominant (a 1 c)-type TD along with basal plane stacking faults and f1120g prismatic stacking faults. Channeling cracks were observed in the GaN film when the AlN buffer layer was not utilized. This was attributed to tensile stress induced from the thermal expansion coefficient mismatch. I. INTRODUCTION
Contributing Editor: Don W. Shaw a) Address all correspondence to this author. e-mail: [email protected] b) This author was an editor of this focus issue during the review and decision stage. For the JMR policy on review and publication of manuscripts authored by editors, please refer to http://www. mrs.org/jmr-editor-manuscripts/ DOI: 10.1557/jmr.2015.210
to the drain near the surface. Such lateral device structures suffer from dynamic on-resistance and current collapse due to surface states, limiting the device performance.7,8 Furthermore, to increase the breakdown voltage in lateral devices necessary for high power modules in HEVs, an increase in the distance between the source and drain is needed, which leads to larger overall chip size.9 Vertically conducting GaN-based power devices offers many advantages over lateral structures which are reaching their limits. 10,11 In a vertical device, the current flows in all areas of the device, consequently, current collapse is suppressed which allows for better device operation.3 In addition, the vertical device configuration is more effective in realizing low on-resistance and high breakdown voltages, achieving much higher power density over lateral device structures. However, the development of vertically conducting GaN-based power devices has been limited due to the absence of viable substrates. The fabrication of vertical GaN-based power devices has been reported on bulk GaN substrates (GaN on GaN),12,13 however, bulk GaN substrates are still limited in terms of size, cost, and availability. Vertically conducting GaN-based devices on SiC (GaN on SiC) is an alternative to GaN on GaN devices. The widespread availability of SiC has enabled the realization of high-f
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