Interface Study of SiO 2 / HfO 2 /SiO 2 Stacks Used as InterPoly Dielectric for Future Generations of Embedded Flash Mem
- PDF / 367,268 Bytes
- 6 Pages / 612 x 792 pts (letter) Page_size
- 17 Downloads / 228 Views
1252-I07-08
Interface study of SiO2/ HfO2/SiO2 stacks used as InterPoly Dielectric for future generations of embedded Flash memories. A. Guiraud 1,2 , N. Breil 3, M. Gros-Jean 1, D. Deleruyelle 2 , G. Micolau 2 , C. Muller 2, N. Chérault 1 and P. Morin 1 1
ST Microelectronics, 850 rue Jean Monnet, 38926 Crolles, France IM2NP UMR CNRS 6242, IMT Technopôle de Château Gombert, 13451 Marseille Cedex 20, France 3 IBM Microelectronics, 850 rue Jean Monnet, 38926 Crolles, France 2
ABSTRACT We have investigated the integration of Hf-based material as Inter Poly Dielectric in flash memories devices. Electrical measurements showed the good properties of SiO2/HfO2/SiO2 stacks. We then interested to the impact of the thermal budget on this specific stack which induces changes in the electrical properties. XPS measurements suggests those changes are due to the presence of an Hf-silicate layer at the SiO2/HfO2 interface. INTRODUCTION: The Flash architecture consists in a MOSFET with a floating gate buried in the oxide. The floating gate is insulated from the silicon by the tunnel oxide and insulated from the control gate by the Inter Poly Dielectric (IPD). The Oxide-Nitride-Oxide (ONO) stack is currently used in Flash memory technology as IPD. Its role is to ensure a good coupling ratio between the control gate and the floating gate allowing program/erase trough tunnel oxide. For future generations of Non-Volatiles Memories (NVM), ONO stack almost reached its scaling limit in terms of leakage current and the use of high-k materials is mandatory in order to maintain (or improve) the coupling ratio after down scaling [1]. For embedded NVM (eNVM) applications, the process must be CMOS compatible. Materials like HfO2 and its silicates (HfSiO, HfSiON) used for highκ metal gate technology seems interesting to use. We keep the top and bottom SiO2 layers because of the high electron barrier for retention in temperature issues as well as a good interface with the poly-Si.
Control gate IPD
Floating gate de Tunnel oxy
Fig.1: Transmission Electron Microscopy (TEM) view of a flash cell
In this paper, we study electrical of SiO2/High-k/SiO2 stacks an try to establish links with physical properties. EXPERIMENT The analyzed samples were MIS capacitors composed of a tri-layer SiO2/HfO2/SiO2, SiO2/HfSiO/SiO2 or SiO2/HfSiON/SiO2 stacks, on the top of which TiN electrodes were patterned. Prior to the high-k material deposition, a 5nm thick High Temperature Oxyde (HTO) SiO2 layer was deposited at 750°C on p-type (100) silicon wafer. The HfO2 layer was then grown by Plasma Enhanced Atomic Layer Deposition (PEALD) using Tetrakis[EthylMethylAmino]Hafnium (TEMAH) precursors and O2 plasma at 250°C. HfSiO layer was deposited by Metal-Organic Chemical Vapor Deposition (MOCVD) at 600°C, Decoupled Plasma Nitridation (DPN) followed by Post Nitridation Anneal (PNA) was performed on some samples to form HfSiON. The high-k layer was subsequently capped with a second 5nm thick HTO SiO2 layer. References ONO samples were processed by Low Pressure Chemical V
Data Loading...
