Introduction to Advanced System-on-Chip Test Design and Optimization
SOC test design and its optimization is the topic of Introduction to Advanced System-on-Chip Test Design and Optimization. It gives an introduction to testing, describes the problems related to SOC testing, discusses the modeling granularity and the imple
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FRONTIERS IN ELECTRONIC TESTING Consulting Editor Vishwani D. Agrawal Books in the series: Embedded Processor-Based Self-Test D. Gizopoulos ISBN: 1-4020-2785-0 Testing Static Random Access Memories S. Hamdioui ISBN: 1-4020-7752-1 Verification by Error Modeling K. Radecka and Zilic ISBN: 1-4020-7652-5 Elements of STIL: Principles and Applications of IEEE Std. 1450 G. Maston, T. Taylor, J. Villar ISBN: 1-4020-7637-1 Fault Injection Techniques and Tools for Embedded systems Reliability Evaluation A. Benso, P. Prinetto ISBN: 1-4020-7589-8 High Performance Memory Memory Testing R. Dean Adams ISBN: 1-4020-7255-4 SOC (System-on-a-Chip) Testing for Plug and Play Test Automation K. Chakrabarty ISBN: 1-4020-7205-8 Test Resource Partitioning for System-on-a-Chip K. Chakrabarty, Iyengar & Chandra ISBN: 1-4020-7119-1 A Designers' Guide to Built-in Self-Test C. Stroud ISBN: 1-4020-7050-0 Boundary-Scan y Interconnect Diagnosis J. de Sousa, P.Cheung ISBN: 0-7923-7314-6 Essentials of Electronic Testing for Digital, Memory, and Mixed Signal VLSI Circuits M.L. Bushnell, V.D. Agrawal ISBN: 0-7923-7991-8 Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4 Test Standard A. Osseiran ISBN: 0-7923-8686-8 Design for At-Speed Test, Diagnosis and Measurement B. Nadeau-Dosti ISBN: 0-79-8669-8 Delay Fault Testing g for VLSI Circuits A. Krstic, K-T. Cheng ISBN: 0-7923-8295-1 Research Perspectives p and Case Studies in System Test and Diagnosis J.W. Sheppard, W.R. Simpson ISBN: 0-7923-8263-3 Formal Equivalence q Checking g and Design Debugging S.-Y. Huang, K.-T. Cheng ISBN: 0-7923-8184-X Defect Oriented Testing for CMOS Analog and Digital Circuits M. Sachdev ISBN: 0-7923-8083-5
INTRODUCTION TO ADVANCED SYSTEM-ON-CHIP TEST DESIGN AND OPTIMIZATION
by
ERIK LARSSON Linköpings University, Sweden
A C.I.P. Catalogue record for this book is available from the Library of Congress.
ISBN-10 1-4020-3207-2 (HB) Springer Dordrecht, Berlin, Heidelberg, New York ISBN-10 0-387-25624-5 (e-book) Springer Dordrecht, Berlin, Heidelberg, New York ISBN-13 978-1-4020-3207-3 (HB) Springer Dordrecht, Berlin, Heidelberg, New York ISBN-13 978-0-387-25624-5 (e-book) Springer Dordrecht, Berlin, Heidelberg, New York
Published by Springer, P.O. Box 17, 3300 AA Dordrecht, The Netherlands.
Printed on acid-free paper
All Rights Reserved © 2005 Springer No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Printed in the Netherlands.
Contents
Preface Acknowledgements Part 1
xiii xvii
Testing concepts
1.
INTRODUCTION
2.
DESIGN FLOW 1 Introduction 2 High-level design 3 Core-Based Design 3.1 Network-on-Chip 3.2 Platform-Based Design 4 Clocking 4.1 System Timing 4.2 Clock Distribution 4.3 Multiple Clock
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