Laser Thermal Induced Crystallization for 20 nm Device Structures
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Laser Thermal Induced Crystallization for 20 nm Device Structures Shenzhi Yang and Michael O. Thompson Dept. Materials Sciences and Engineering, Cornell University, Ithaca, NY 14853
ABSTRACT: The melt kinetics of shallow junction formation by laser thermal processes has been studied using transient conductance measurements. The melt and solidification dynamics of 20 nm amorphous layers were measured and shown to follow behaviors predicated by deeper melts, including explosive crystallization and interface bounce back. The effects of surface barrier oxides and metal absorber layers, required for CMOS process integration, were examined and shown to be nearly negligible. Quantitative evaluation of a device process window by these measurements was in good agreement with sheet resistance results. Finally, the effect of the buried oxide in SOI structures was investigated. Solidification velocities in such structures were reduced by a factor of three as compared with bulk silicon.
INTRODUCTION: The scaling of MOSFET dimensions into sub-100 nm regimes requires increasingly precise control of the critical device dimensions, including source/drain shallow junctions. As the devices shrink, short channel effect and linkup resistances to the channel severely degrade performance [1]. To suppress these effects, the ITRS predicts that junction depths must approach 20 nm coupled with junction abruptness on the nanometer scale [2]. Simultaneously, the sheet resistances cannot increase substantially requiring that activated doping levels in the source and drain increase to beyond solid solubility limits. While there is continued advancement in fast ramp RTA and spike annealing, these techniques are fundamentally limited by thermodynamic equilibrium and point defect enhanced diffusion and will have difficulties reaching (anticipated) requirements beyond the 100 nm ITRS node [2,3]. Only selective epitaxy and laser thermal processing (LTP) have demonstrated the non-equilibrium doping concentrations and abrupt profiles required [4,5]. In LTP, an amorphous layer formed at the surface determines the junction depth. This layer is formed either by the impurity implant itself (i.e. arsenic) or by a preamorphization Si or Ge implant to 20-30 nm depth followed by a low energy implant (i.e. boron). Pulsed laser irradiation induces a surface melt with solidification trapping impurities on substitutional and electrically active sites [6]. Because of the melting temperature difference between amorphous and crystalline silicon [7], there is a process window that melts only the amorphous layer and not the underlying substrate. As impurity diffusion in the liquid phase is extremely rapid, dopants are uniformly distributed throughout the melt leading to an abrupt junction defined by the amorphous layer. This technique is able to form very shallow abrupt junctions with activated dopant concentrations well above the equilibrium solid solubility [4,5]. However, process integration issues require the addition of a barrier oxide and metal absorber layer ov
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