Lattice-Mismatch Strain and Confinement in Nanoscale Si/SiO 2 Structures Fabricated Using Thermal Oxidation
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MRS Advances © 2019 Materials Research Society DOI: 10.1557/adv.2019.124
Lattice-Mismatch Strain and Confinement in Nanoscale Si/SiO2 Structures Fabricated Using Thermal Oxidation Erin I. Vaughan1, Clay S. Mayberry1, Danhong Huang1,2, Ashwani K. Sharma1,2 1
Air Force Research Laboratory, Space Vehicles Directorate, Kirtland AFB, Albuquerque, NM, 87117, USA
2 Electrical and Computer Engineering Department, University of New Mexico, 1 University of New Mexico, Albuquerque, NM 87131, USA
ABSTRACT
The behavior of electron and hole transport in semiconductor materials is influenced by lattice-mismatch at the interface. It is well known that carrier scattering in a confined region is dramatically reduced. In this work, we studied the effects of coupling both the strain and confinement simultaneously. We report on the fabrication and characterization of nanoscale planar, wall-like, and wire-like Si/SiO2 structures. As the Si nanostructure dimensions were scaled down to the quantum regime by thermal oxidation of the Si, changes to the band structure and carrier effective mass were observed by both optical and electrical techniques. Transient-time response measurements were performed to examine the carrier generation and recombination behavior as a function of scaling. Signal rise times decreased for both carrier types by an order of magnitude as Si dimensions were reduced from 200 to 10 nm, meaning that the carrier velocity is increasing with smaller scale structures. This result is indicative of decreased Si bandgap energy and carrier effective mass. Photoluminescence measurements taken at 50K showed changes in the PL response peak energies, which illustrates changes in the band structure, as the Si/SiO2 dimensions are scaled.
INTRODUCTION: Nanowire devices are rapidly becoming recognized for their promising potential applications in the CMOS industry. The need for increasing numbers of microprocessor components to fit inside ever shrinking devices is growing at an
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exponential rate. To meet this demand, the integrated circuit components, i. e. transistors, must also shrink down dramatically, and recent advances in nanowire technology appear to offer the solution. In addition to reducing the transistor channel length, improving the speed at which the components operate is also of great interest. A combination of reduced device dimensions and added strain has been theorized to enhance the transport characteristics of the charge carriers. The motion of a charge carrier in a crystal lattice is dependent on the effective mass value (m*), which is related to the carrier mobility (μ) and the effective carrier lifetime (τeff) by Equation 1. Ɋൌ
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(1)
where τeff accounts for contributions from all scattering mechanisms. Because of the combined effects of confinement and
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