Oxidation of Si nanocrystals fabricated by ultra-low energy ion implantation in thin SiO 2 layers
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Oxidation of Si nanocrystals fabricated by ultra-low energy ion implantation in thin SiO2 layers H. Coffin1, C. Bonafos1, S. Schamm1, N. Cherkashin1,2, M. Respaud3, G. Ben Assayag1, P. Dimitrakis4, P. Normand4, M. Tencé5, C. Colliex5 and A. Claverie1 1
CEMES-CNRS, 29 rue J. Marvig, 31055, Toulouse, France Ioffe Physico-Technical Institute, Polytekhnicheskaya 26, St Petersburg, 194021, Russia 3 LNMO, INSA, Département de Physique, 135 avenue de Rangueil, 31077 Toulouse France 4 Institute of Microelectronics, NCSR 'Demokritos', 15310 Aghia Praskevi, Greece 5 Laboratoire de Physique des Solides, Université Paris-Sud -UMR 8502, 91405 Orsay, France 2
ABSTRACT The effect of annealing in diluted oxygen on the structural characteristics of thin silicon dioxide layers with embedded Si nanocrystals fabricated by ultra-low energy ion implantation (1 keV) is reported. The nanocrystal characteristics (size, density, coverage) have been measured by spatially resolved Electron Energy Loss Spectroscopy using the spectrum-imaging mode of a Scanning Transmission Electron Microscope. Their evolution has been studied as a function of the annealing duration under N2+O2 at 900°C. An extended spherical Deal-Grove model for the self-limiting oxidation of embedded silicon nanocrystals has been carried out. It shows that stress effects, due to the deformation of the oxide, slows down the chemical oxidation rate and leads to a self-limiting oxide growth. The model predictions show a good agreement with the experimental results. INTRODUCTION Oxidised silicon nanocrystals (ncs) embedded within the gate oxide of a metal-oxidesemiconductor field effect transistor (MOSFET) are of great interest due to their possible applications in the microelectronic industry. Indeed, low-power non-volatile memories with long retention times can be obtained using nanocrystals [1]. Floating gates consisting of Si or Ge ncs can be fabricated either using deposition techniques [1, 3], thermal oxidation of Si1-xGex [4] or ion implantation followed by annealing [5]. The possibility of fabricating ncs memory devices by using ultra-low energy Si implantation and subsequent thermal treatment has been recently demonstrated [6, 7]. This fabrication route is very attractive because of its ability to control the size and the depth-location of a narrow band of nanocrystals and its compatibility with standard CMOS technology. In practice, high dose (typically 1016 cm-2) Si implantation in the 1 keV range in very thin (> 2 + . As a consequence, the oxidation process only depends on ks, the surface bD ks b h reaction rate and therefore is reaction-limited. COMPARISON THEORY/EXPERIMENTS Concerning the evolution of the ncs mean radius during oxidation, we obtain a good agreement between our model and the experimental data (see Fig. 2) for a viscosity of 7x1014 poises and for α of the order of magnitude of the one proposed in refs [9, 11]. While the value taken for α has little impact on the result of calculation, this is not the case for the viscosity. The smaller the vi
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