Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs
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Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs Akin Gokalan1 · Suleyman Tosun1
· Deniz Dal2
Received: 17 January 2020 / Accepted: 16 November 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Designing an application in hardware under inversely competing constraints such as area and performance with different objective functions such as power consumption and reliability of the circuits is a cumbersome task. Having different versions of the same resource type during the design process may ease this burden since there can be several alternative resources to meet the given constraints. In this paper, we characterize a library of some commonly used arithmetic circuits in FPGAs in terms of the speed, area, power consumption, and vulnerability to error propagation as the reliability parameter. Specifically, we implemented four well-known adders and two multipliers in an SRAM-based FPGA that is a part of Xilinx’s Zynq-7000 SoC platform. We then injected errors to the configuration bits of the circuits to evaluate the error propagation. The results show that different versions of the same resources can have different reliability values in addition to the area, latency, and power values. Keywords Soft error · FPGA · Reliability · Arithmetic circuits
1 Introduction 1.1 Motivation A Field Programmable Gate Array (FPGA) is an electronic device that consists of a large number of configurable logic blocks (CLBs), programmable routing switches that connect the CLBs, and input-output (IO) pins [26]. In FPGAs, logic functions are realized utilizing CLBs, which in turn are composed of look-up tables (LUTs) that store the truth tables of the functions, multiplexers, and
Responsible Editor: A. Orailoglu Suleyman Tosun
[email protected] Akin Gokalan [email protected] Deniz Dal [email protected] 1
Department of Computer Engineering, Hacettepe University, Ankara, Turkey
2
Department of Computer Engineering, Ataturk University, Erzurum, Turkey
flip-flops. FPGAs’ prevalence is growing in both industry and academia due to their advantages, such as reduced time-to-market, reconfigurability, and parallel processing ability. They are also preferred as the choice of the design platform in aerospace industries [20]. However, under ionizing radiation, the configuration bits of the FPGAs tend to flip, which is called SEU (single event upset) [1]. An SEU may propagate through the circuit and cause unexpected behaviour. On the other hand, it may not change the output of the design due to the error-masking capabilities of the combinational circuits. In other words, the internal structure of the circuit and the input pattern applied determine whether or not the behaviour changes in the presence of an SEU. SEU, by definition, is a change of state in a semiconductor that does not permanently change the circuit’s behavior. If such a non-persistent error causes the data stored in memory to be erroneous even for a short period, all operation
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