Linewidth Dependence of the Reverse Bias Junction Leakage for Co-Silicided Source/Drain Junctions
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Linewidth dependence of the reverse bias junction leakage for Co-silicided source/drain junctions Anne Lauwers, Muriel de Potter, Richard Lindsay, Oxana Chamirian, Caroline Demeurisse, Christa Vrancken and Karen Maex IMEC, Kapeldreef 75, 3001 Leuven, BELGIUM ABSTRACT In this work the reverse bias junction leakage was studied for Co-silicided 100 nm deep As source/drain junctions. The effect of pre-clean and silicidation temperature was investigated. The area component of the leakage current was found to be dominant for silicided source/drain areas wider than 1 µm. Increasing the thermal budget for silicidation was found to improve the area leakage. For diodes consisting of active area stripes narrower than 0.5 µm, the leakage current is no longer improved by increasing the silicidation temperature. As a result the leakage current is found to depend strongly on the active area linewidth. It was found that the linewidth dependence of the junction leakage cannot be attributed to silicide induced stress. It is argued that the higher leakage current observed for narrow lines can be attributed to the stress induced by the STI isolation and to increased silicide thickness in the narrow active lines INTRODUCTION At the moment Co-silicide is the preferred self-aligned silicide for sub 0.25 µm CMOS technologies. To be compatible with the continuously decreasing junction depth, the Co-silicide film thickness is being scaled down to lower the Si consumption at the expense of a higher sheet resistance. To optimally balance the trade-off between silicide sheet resistance and junction leakage, it is crucial to minimise the silicide/silicon interface roughness. The interface roughness can be improved by optimising the salicide pre-clean and the thermal budget of silicidation. [1] In this work the reverse bias junction leakage is studied for Co-silicided 100 nm deep As source/drain junctions defined by shallow trench isolation. The junction leakage is studied as a function of the active area width for different trench widths. The effect of pre-clean and silicidation temperature is investigated. EXPERIMENTAL DETAILS For this experiment p-type device quality wafers with 200 mm diameter have been used. Source/drain areas were defined by 400 nm deep shallow trench isolation. Highly doped As junctions were obtained by implantation of 4E15 As/cm2 at an energy of 25 keV followed by spike RTP anneal at 1100ºC. Co-silicide was formed by 2-step silicidation from a Co/Ti bilayer and resulting Co-silicide film thickness is 25 nm. Prior to Co/Ti deposition the residual oxide is removed by HF pre-clean (90 sec dip in 2% HF followed by rinse/dry) or by SSE pre-clean (Soft Sputter Etch = Ar bombardment). The temperature of the second RTP step of Co-silicidation is
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