Low-Power Analog Bus for System-on-Chip Communication
At present, performance and efficiency of a system-on-chip (SoC) design depends significantly on the on-chip global communication across various modules on the chip. System-on-chip communication is generally implemented using a bus architecture that runs
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Abstract At present, performance and efficiency of a system-on-chip (SoC) design depends significantly on the on-chip global communication across various modules on the chip. System-on-chip communication is generally implemented using a bus architecture that runs very long distances and covers significant area of the integrated circuit. The difficult challenges in design of a large SoC such as one containing many processor cores include routing complexity, power dissipation, hardware area, latency, and congestion of the communication system. This paper proposes an analog bus for digital data. In this scheme, it replaces ‘n’ wires of an ‘n’-bit digital bus carrying data between cores with just one (or a few) wire(s) carrying analog signal(s) encoding ‘2n’ voltage levels. This analog bus uses digital-to-analog converter (DAC) drivers and analog-to-digital converter (ADC) receivers. This on-chip communication proposal can potentially save power and area. Diminution in the number of wire lines saves chip area and the reduction in total intrinsic wire capacitance consequently reduces the power consumption of the bus. The scheme should also reduce signal interference and cross-talk by eliminating the need for multiple line drivers and buffers. In spite of over-heads of the ADCs and DACs, this scheme provides significant power saving. Linear technology SPICE simulations show that the ratio of the power of the bus consumed by the proposed analog scheme to a typical digital scheme (without bus encoding or differential signalling) is given by Panalog/Pdigital = 1/(3n) where ‘n’ is the width of the bus. Keywords System-on-Chip
Routing Communication Energy Power
V.R. Jillella (&) Vignan Institute of Technology and Science, Hyderabad, India e-mail: [email protected] S.R. Parvataneni Vignan Institute of Management and Technology for Women, Hyderabad, India e-mail: [email protected] © Springer Science+Business Media Singapore 2016 H.S. Saini et al. (eds.), Innovations in Computer Science and Engineering, Advances in Intelligent Systems and Computing 413, DOI 10.1007/978-981-10-0419-3_15
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V.R. Jillella and S.R. Parvataneni
1 Introduction In present ICs, power was a second order concern in chip design, succeeding the first order concerns of timing, area, testability, and cost. Nevertheless, for most system-on-chip (SoC) IC designs, low power dissipation is now one of the most momentous chip design purposes of any IC design. As power reduction is a product of overall improvement of the technology, it is not achieved through a single technological improvement. When the feature size is reduced down to the deep sub-micron region and power consumption is decomposed between the functional blocks and the communication paths between them, the power consumption has become a principal component. In relation with the multiple cores in the die, there is lack of literature on designing interconnect framework. Interconnect layout was done very late in the overall design because the conventional design flow was mostly logic
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