SPI Bus
The Serial Peripheral Interface bus, known affectionately as spy, is a synchronous serial interface that was named by Motorola.18 The SPI protocol operates in full-duplex mode, allowing it to send and receive data simultaneously. Generally speaking, SPI h
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SPI Bus The Serial Peripheral Interface bus, known affectionately as spy, is a synchronous serial interface that was named by Motorola.18 The SPI protocol operates in full-duplex mode, allowing it to send and receive data simultaneously. Generally speaking, SPI has a speed advantage over the I2C protocol but requires more connections.
SPI Basics Devices on the SPI bus communicate on a master/slave basis. Multiple slaves coexist on a given SPI bus, with each slave being selected for communication by a slave select signal (also known as chip select). Figure 16-1 shows the Raspberry Pi as the master communicating with one slave device. Additional slaves would be connected as shown with the exception that a different slave select signal would be used.
Figure 16-1. SPI interface © Warren Gay 2018 W. Gay, Advanced Raspberry Pi, https://doi.org/10.1007/978-1-4842-3948-3_16
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Data is transmitted from the master to the slave by using the MOSI line (master out, slave in). As each bit is being sent out by the master, the slave simultaneously sends data on the MISO line (master in, slave out). Bits are shifted out of the master and into the slave, while bits are shifted out of the slave and into the master. Both transfers occur to the beat of the system clock (CLK). Many SPI devices support only 8-bit transfers, while others are more flexible. The SPI bus is a de facto standard, meaning that there is no standard for data transfer width and SPI mode.18 The SPI controller can also be configured to transmit the most significant or the least significant bit first. All of this flexibility can result in confusion.
SPI Mode SPI operates in one of four possible clock signaling modes, based on two parameters: Parameter Description CPOL
Clock polarity
CPHA
Clock phase
Each parameter has two possibilities, resulting in four possible SPI modes of operation. Table 16-1 lists all four available modes. Note that a given mode is often referred to by using a pair of numbers like 1,0 or simply as mode 2 (for the same mode, as shown in the table). Both references types are shown in the Mode column.
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Table 16-1. SPI Modes CPOL
CPHA
Mode
Description
0
0
0,0
0
Noninverted clock, sampled on rising edge
0
1
0,1
1
Noninverted clock, sampled on falling edge
1
0
1,0
2
Inverted clock, sampled on rising edge
1
1
1,1
3
Inverted clock, sampled on falling edge
Clock Sense
Description
Noninverted
Signal is idle low, active high
Inverted
Signal is idle high, active low
Peripheral manufacturers did not define a standard signaling convention in the beginning. Consequently SPI controllers often allow configuration of any of the four modes while the remaining only permit two of the modes. However, once a mode has been chosen, all slaves on the same bus must agree.
Signaling The clock polarity determines the idle clock level, while the phase determines whether the data line is sampled on the rising or falling clock signal. Figure 16-2 shows mode 0,0, which is perhaps the
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