Low-Power Variation-Tolerant Design in Nanometer Silicon
Low-Power Variation-Tolerant Design in Nanometer Silicon Edited by: Swarup Bhunia Saibal Mukhopadhyay Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design te
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Swarup Bhunia · Saibal Mukhopadhyay Editors
Low-Power Variation-Tolerant Design in Nanometer Silicon
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Editors Swarup Bhunia Department of Electrical Engineering and Computer Science Case Western Reserve University Cleveland, OH 44106-7071, USA [email protected]
Saibal Mukhopadhyay School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta, GA 30332-0250, USA [email protected]
ISBN 978-1-4419-7417-4 e-ISBN 978-1-4419-7418-1 DOI 10.1007/978-1-4419-7418-1 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2010938792 © Springer Science+Business Media, LLC 2011 All rights reserved. This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
Preface
The energy required for running integrated circuits (ICs) is increasing in every new generation of electronic systems. At the same time the manufacturing process used to build these ICs are becoming less deterministic. Hence, low-power design under large parameter variations has emerged as an important challenge in the nanometer regime. The book, for the first time, integrates description of low power and variation issues and provides design solutions to simultaneously achieve low power and robust operation under variations. Design considerations for low power and robustness with respect to variations typically impose contradictory requirements. Power reduction techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book introduces the specific challenges associated with low power and variation-tolerant design in the nanometer technology regime at different levels of design abstraction. It considers both logic and memory design aspects and encompass modeling, analysis as well as design methodology to simultaneously achieve low power and variation tolerance while minimizing design overhead. The issue of device degradation due to aging effects as well as temporal variation in device parameters due to environmental fluctuations are also addressed. Micro-architecture level design modifications, subthreshold design issues, statistical design approaches, design of low-power and robust digital signal processing (DSP) hardware, analog and mixed-signal circuits, reconfigurable com
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