Low Temperature Process Technologies for the Next Generation High Performance Polycrystalline Silicon Thin-Film Transist
- PDF / 273,838 Bytes
- 12 Pages / 612 x 792 pts (letter) Page_size
- 9 Downloads / 178 Views
Low Temperature Process Technologies for The Next Generation High Performance Polycrystalline Silicon Thin-Film Transistors Seiichiro Higashi, Daisuke Abe, Satoshi Inoue and Tatsuya Shimoda Base Technology Research Center, Seiko Epson Corp. Nagano, 392-8502 JAPAN ABSTRACT Low temperature process technologies for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) are discussed based on the investigations of pulsed laser crystallization, plasma treatment of poly-Si films, and SiO2/Si interface formation. Although high density (~1018 cm-3) trap states localized at grain boundaries are introduced to the poly-Si films by laser crystallization, they are efficiently decreased to the order of 1016 cm-3 by following hydrogen plasma treatment. It is also shown that high quality SiO2/Si interfaces with the density of interface trap states (Dit) in the order of 1010 cm-2eV-1 are achieved using electron cyclotron resonance (ECR) plasma enhanced chemical vapor deposition (PECVD). By applying these low temperature process technologies to the fabrication process, high performance poly-Si TFTs with high n-channel mobility (µn) of 187 cm2V-1s-1, low threshold voltage (Vth) of 1.97 V and small subthreshold swing (S) of 210 mV/dec. were obtained. These results indicate that the development of low temperature process technologies that can control trap states is the key to the next generation high performance poly-Si TFTs.
INTRODUCTION Low temperature process poly-Si TFTs have successfully applied to liquid crystal displays (LCDs) and organic light emitting diode (OLED) displays [1-3]. In addition to the display applications, they have applied to other electronic devices of sensors [4] and memories [5]. Recently, the idea of integrating these electronic devices monolithically on the peripheral part of the display, which is called system on panel (SOP), is proposed. If we can realize these sophisticated electronic devices, poly-Si TFTs may create a huge application field in the near future. In order to make the idea to a real one, improving the performance of poly-Si TFTs is the most important technological issue. We absolutely need higher mobility and lower threshold voltage poly-Si TFTs. Looking into the low temperature fabrication process of poly-Si TFTs, one can point out D12.6.1
several key technologies that are responsible for the performance of TFTs. They are poly-Si active layer formation and SiO2/Si interface formation technologies. Pulsed laser crystallization of Si thin films is widely used for the poly-Si formation and PECVD is used for SiO2/Si interface formation. These conventional low temperature processes introduce large amount of trap states to the MOS structure of TFTs. Due to our limited thermal budget, it is difficult to remove these trap states by means of thermal treatments and they are active even after TFT fabrication process is completed. Carriers induced by gate electric field are trapped by the trap states and they cannot contribute to conduction. We are required higher gate volta
Data Loading...
