LPCVD Deposition Techniques for Nanograin sub-10nm Polysilicon Ultra-thin Films
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LPCVD deposition techniques for nanograin sub-10nm polysilicon ultra-thin films Serge Ecoffey, Didier Bouvet, Adrian M. Ionescu and Pierre Fazan Swiss Federal Institute of Technology, Electronic Laboratories, CH-1015 Lausanne, Switzerland ABSTRACT This paper investigates the limits of a low pressure chemical vapour deposition (LPCVD) technique for the deposition of a nanometre scale ultra-thin polysilicon (poly-Si) film with sub10nm grain sizes. Three different processes using pure silane (SiH4) in a standard horizontal hotwall reactor are presented: (i) a direct poly-Si deposition, (ii) a Hemispherical Silicon Grain (HSG) deposition and (iii) an amorphous silicon (a-Si) deposition followed by a thermal crystallization anneal. The direct poly-Si deposition gives a minimum film thickness achievable around 20 nm with grain sizes ranging from 20 to 30 nm. The HSG deposition process leads to the formation of grains with diameters varying from 5 to 50 nm and heights ranging from 5 to 20 nm. The best results are obtained with the third process (a-Si / crystallization), which allows the formation of 6 nm poly-Si thick films with grain sizes ranging from 10 to 20 nm. INTRODUCTION According to the 1999 International Technology Roadmap for Semiconductors (ITRS) [1], it is recognized that “no known solutions” in virtually all of the technology areas will be encountered by 2008 with the shrinkage of the feature size in integrated circuits below 20 – 30 nm. Single Electron Devices (SED) are projected to be alternative components for ultra-large scale integration (ULSI). Present temperature operation of SED's is less than 20K, but room temperature operated memories have already been demonstrated [2-5]. In those devices, the transfer of a single electron is made possible thanks to the Coulomb blockade effect [6]. To be efficient at room temperature, the Coulomb blockade needs nanometer size devices that cannot be achievable with actual lithographic limitations. Therefore most of the SE memories [2-5] consist of nanometer scale separated Si islands that can store a charge of one electron per island. A recent work on a poly-Si wire in which each grain represents an island [7] let us think that an ultra-thin poly-Si wire with nanograins could be an alternative for those devices. In this case, it clearly appears that the critical technological step lies in the deposition of an ultra-thin poly-Si film with grain sizes of less than 10 nm. This paper presents the evaluation of three different LPCVD processes to achieve the deposition of an ultra-thin nanograin poly-Si film: (i) a direct poly-Si deposition, (ii) a HSG deposition and (iii) an a-Si deposition followed by a crystallization thermal annealing. EXPERIMENTAL DETAILS All the depositions were completed on 100 mm ‹100› oriented, boron-doped p-type silicon wafers with a 70 Å thick silicon dry oxide grown on the surface. The LPCVD system is a conventional horizontal hot wall reactor using pure silane as reactant gas. In the following, three different processes are reported. The poly-
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