Materials challenges in three-dimensional integrated circuits
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Materials challenges The miniaturization of semiconductor devices has been the driving force for research and development (R&D) in the microelectronics industries in the last several decades. This trend has resulted in the high usage of electronic devices in all aspects of daily life, manifested by the current ubiquitous presence of consumer electronic products. Nevertheless, in the near future, we will face the size limits of mobile devices, the need for higher power, and an increase in functional applications. Today, the iPhone is about six inches in length. As mobile phone technology develops to meet user expectations for more functions, increased power will be required. The amount of power available to a mobile phone is limited by the battery size, which cannot be too big, as well as by heat generation, which cannot be too high. It is unlikely that consumers will want future iPhones to increase much more in size. In addition to user demands for a smaller form, high reliability and low cost are also current, urgent challenges for materials selection and integration. The current basic designs of two-dimensional (2D) chip technology and packaging technology need to be reviewed such that future technology can address these challenges with high yield and reliability. Recently, three-dimensional integrated circuits (3D ICs) have become a strong candidate to meet these challenges. Three-dimensional ICs are based on vertical integration, where two or more electronic components are homogenously
or heterogeneously stacked and can be formed by chip-to-chip, chip-to-wafer, or wafer-to-wafer stacking.1 In 2D ICs, the interconnects are horizontal and long, but in 3D ICs, most of the horizontal interconnects are replaced by short vertical interconnects. This not only offers high density integration, but also introduces heterogeneous integration of different functional materials and devices.2 The endeavors of scientists and engineers have advanced 3D ICs from a research topic to the solution of certain advanced commercial products, such as complementary metal-oxide semiconductor (CMOS) image sensors, field-programmable gate arrays, and memories.3 An optical cross-sectional image of a test sample of the stacking of three components—two Si chips and a laminate substrate—is shown in Figure 1. The first level (lower) Si chip has Cu through-silicon via (TSV) technology. There are three levels of solder joints: a ball grid array of 250 µm diameter on the bottom row (unclear due to offset of the crosssection), flip-chip solder joints of 100 µm diameter in the middle, and microbumps of 20 µm diameter on the top, which are between two Si chips. Figure 2 shows a synchrotron radiation tomography image of one 3D IC device sample. The blue arrows show the applied current path during an electromigration test to find the weak link for the system-level reliability. Electromigration is the enhanced atomic diffusion driven by a high electric current density. It induces open or short failures in metallic interconnects in microelectronic devices.
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