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Sung Hwan Chung Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907; and School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907

Bong-Joong Kimb) Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907; and School of Materials Engineering, Purdue University, West Lafayette, Indiana 47907

Minghao Qi Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907; and School of Electrical and Computer Engineering, Purdue University, West Lafayette, Indiana 47907

Xianfan Xu Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907; and School of Mechanical Engineering, Purdue University, West Lafayette, Indiana 47907

Eric A. Stachb) Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907; and School of Materials Engineering, Purdue University, West Lafayette, Indiana 47907

Chen Yangc) Department of Chemistry, Purdue University, West Lafayette, Indiana 47907; and Department of Physics, Purdue University, West Lafayette, Indiana 47907 (Received 11 April 2011; accepted 19 August 2011)

The direct integration of Ge nanowires with silicon is of interest in multiple applications. In this work, we describe the growth of high-quality, vertically oriented Ge nanowires on Si (111) substrates utilizing a completely sub-Au–Si-eutectic annealing and growth procedure. With all other conditions remaining identical, annealing below the Au–Si eutectic results in successful heteroepitaxial nucleation and growth of Ge nanowires on Si substrate while annealing above the Au–Si eutectic leads to randomly oriented growth. A model is presented to elucidate the effect of the annealing temperature, in which we hypothesized that sub-Au–Si-eutectic annealing leads to the formation of a single and well-oriented interface, essential to template heteroepitaxial nucleation. These results are critically dependent on substrate preparation and lead to the creation of integrated nanowire systems with a low thermal budget process.

I. INTRODUCTION

Current address: Semiconductor Division, Samsung Electronics Co. Ltd., Gyeonggido, South Korea b) Current address: Center for Functional Nanomaterials, Brookhaven National Laboratory, Upton, New York 11973 c) Address all correspondence to this author. e-mail: [email protected] DOI: 10.1557/jmr.2011.313

relatively low-growth temperature (below 400 °C), and compatibility with current silicon VLSI technology. The widely accepted growth mechanism for the creation of Ge nanowires is the vapor–liquid–solid (VLS) mechanism. During VLS nanowire growth, a vapor phase precursor for Ge—such as GeH4 or Ge2H6—decomposes catalytically at the surface of a metal nanoparticle (most often one with which it forms a binary eutectic) and then dissolves into the metal nanoparticle to form a molten alloy. The continuous supply of Ge from the vapor phase results in supersaturation of Ge within the liquid alloy nanoparticle, and leads first to nucleation and then axial growth of the nanowir