Mechanisms of Low-Temperature Ti/Si-Based Wafer Bonding
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Mechanisms of Low-Temperature Ti/Si-Based Wafer Bonding Jian Yu, Yinmin Wang*, Arthur W. Haberl**, Hassa Bakhru**, Jian-Qiang Lu, and Ronald J. Gutmann Focus Center – New York, Rensselaer, Rensselaer Polytechnic Institute, Troy, NY *Lawrence Livermore National Laboratory, Livermore, California 94551 **University at Albany-SUNY, Albany, New York 12203 ABSTRACT Three-dimensional (3D) wafer-level integration is receiving increased attention with various wafer bonding approaches being evaluated. Recently, we explored an alternative lowtemperature Ti/Si-based wafer bonding, in which an oxidized silicon wafer was successfully bonded with a prime silicon wafer at 400°C using 30 nm sputtered Ti as adhesive. The bonded pairs show excellent bonding uniformity and mechanical integrity. Rutherford backscattering spectrometry (RBS) was applied to confirm the interdiffusion occurred in the interlayer. The bonding interface was examined by high-resolution transmission electron microscopy (HRTEM) assisted with electron energy loss spectroscopy (EELS) elemental mapping and energy dispersive X-ray spectroscopy (EDX). Characterization of the bonding interface indicates the strong adhesion achieved is attributed to an amorphous layer formed by interdiffusion of Si and oxygen into Ti interlayer and the unique ability to reduce native oxide (SiO2) by Ti even at low temperatures. INTRODUCTION Three-dimensional (3D) wafer-level integration is receiving increased attention [1-3]. Bonding of pre-processed device wafers at back-end-of-the-line (BEOL) compatible conditions (≤450°C) has been considered as one of the promising approaches to realize 3D structures. A schematic 3D concept based on wafer bonding technology is shown in Figure 1 [2]. Various lowtemperature bonding approaches are currently being evaluated, including oxide-to-oxide [1], dielectric adhesive [2] and copper-to-copper [3] wafer bonding. Since each has limitations and technical issues, it is premature to determine which will dominate for different applications. Bridge Via Plug Via Recently, we reported nearly void-free 200 Dielectric mm wafer bonding using ultra-thin titanium (Ti) 3rd Level Substrate Device (Thinned as adhesive [4]. A simplified bonding scheme surface Substrate) was tested (Figure 2), in which an oxidized Si Bond wafer deposited with approximately 30-nm Ti Dielectric (Face-to-back) 2nd Level Substrate (namely “wafer I”) was bonded with a prime Si Device (Thinned surface Substrate) wafer (“wafer II”) in vacuum (1.5x10-4 torr) at 400°C for 2 hours with 10 kN down-force Bond (Face-to-face) applied. The bonded pairs successfully passed a Multi-level on-chip interconnects 1st Level Device series of mechanical integrity tests, showing surface Substrate sufficient bonding strength to accommodate Figure 1. Schematic of 3D concept based downstream processes (e.g., backside thinning on wafer bonding technology [2]. and die sawing). The advantage of using an oxidized Si wafer on “wafer I” side is that the
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Si substrate (wafer I) Thermal oxide (300 nm
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