Silicon Layer Stacking Enabled by Wafer Bonding
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0970-Y04-01
Silicon Layer Stacking Enabled by Wafer Bonding Chuan Seng Tan1,2, Kuan-Neng Chen1,3, Andy Fan1, Anantha Chandrakasan1, and Rafael Reif1 1 MIT, Cambridge, MA, 02139 2 Nanyang Technological University, Singapore, 639798, Singapore 3 IBM Research, Yorktown Heights, NY, 10598
ABSTRACT Three-dimensional integrated circuits (3-D ICs), in the form of a vertical stack of several interconnected device layers, have many performance, form factor, and integration advantages. The main objective of this work is to develop reliable process technology to enable the fabrication of a vertically interconnected silicon multi-layer stack. Low temperature wafer bonding processes, both copper thermo-compression bonding and silicon dioxide fusion bonding, are studied extensively as key enabling technology. Cu thermocompression bonding is studied for its feasibility as a permanent bond between active layers in a multi-layer stack. Silicon dioxide wafer bonding, on the other hand, is used as a temporary bond to attach a donor wafer to a handle wafer during donor wafer thinning and subsequent layer transfer. Sufficiently high bond strength is obtained with careful surface preparation and activation prior to bonding. Silicon layer can be stacked either in a “face down” or “face up” orientation. Using a combination of wafer bonding and thinning, double-layer stacks in both orientations are fabricated. By repeating these steps on two “face down” double-layer stacks, a four-layer stack is successful demonstrated. INTRODUCTION While dimensional scaling has consistently improved device gate switching delay, it has a reverse effect on global interconnects [1]. The global interconnects RC delay has increasingly become the circuit performance limiting factor from one technology node to another. Even though Cu/low-κ material systems have been introduced to improve the interconnects RC delay, they are not a long-term solution. This is because the diffusion barrier material used in Cu metallization is of a finite thickness and has higher resistivity than Cu resulting in a higher effective resistivity than bulk Cu. The surface electron scattering effect and high operating temperature make the situation worse [2]. When chip size continues to increase to accommodate more functionality, the total interconnects length increases at the same time. This causes tremendous amount of power being dissipated unnecessarily in the interconnects. On chip signals also require more clock cycles to travel across the entire chip as a result of increasing chip size and operating frequency. To seek a long-term solution, the ITRS has outlined 3-D interconnects as one of the promising options that allows shorter global interconnects and hence improved RC delay [3]. Shorter global interconnects can also lower power dissipation. System-on-a-chip (SoC) is a potential solution to the mounting demand for functionality on a
single chip. There are a few challenges associated with planar implementation of system-on-achip (SoC) on a single substrate. Each functional blo
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