Megavolt Bioron and Arsenic Implantation into Silicon
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MEGAVOLT BIORON AND ARSENIC IMPLANTATION INTO SILICON
P.F. Byrne', N.W. Cheung, S. Tam 2, C.Hu,
Y.C. Shih, J. Washburn, and M. Strathman5 University of California, Berkeley, California 94720 1. current address LSI Logic Corp., Santa Clara, CA 2. current address Intel Corp., Santa Clara, CA 3. current address Charles Evans and Assoc., San Mateo, CA Abstract Formation of buried p-type and n-type layers in (100) silicon has been accomplished by implanting with 4 MeV boron and 11 MeV arsenic ions respectively. The projected range (R.) of 4 MeV boron is 5.2 microns with a straggle (ARN) of .2 microns. The 11 MeV arsenic implant has a R. of 4.37 microns with a ARP of .37 microns. The 4 MeV boron implant was carried out to a dose of 2 lx 1015/ cm 2 while the 11 MeV arsenic implant dose was 1.9x1015/ cm . For both dopants the target holder could be cooled with either liquid nitrogen (LN) or flowing room temperature water (RT). Buried amorphous regions are seen by cross sectional transmission electron microscopy (XTEM) for both boron and arsenic when LN cooling is used. Arsenic shows a buried amorphous region for the RT case as well. The extent of the buried amorphous regions are compared with the energy deposited into nuclear stopping as determined by computer simulation. Threshold levels are determined for the creation of these buried0 amorphous regions. The boron samples were annealed for 30 minutes at 900 C in a nitrogen ambient, and XTEM shows no residual damage for both cooling conditions. The arsenic samples underwent a two step annealing procedure; 545*C for 16 hours followed by a 945*C step for 15 minutes. Regions containing dislocation networks are observed by XTEM for both cooling conditions. The 4 MeV implanted boron buried layer was applied to an NMOS process. Transistors fabricated above the p-type buried layer show channel mobility, threshold voltage, and sub-threshold leakage which are indistinguishable from transistors fabricated without the buried layer. Vertical npn bipolar transistors have been fabricated using the 11 MeV arsenic buried layer to form the collector. Electrical characteristics from both these devices indicate that megavolt ion implantation can be applied to silicon for active device geometries. Introduction Ion implantation in the conventional energy range of 100 to 400 keV has replaced silicon doping through thermal processes for many integrated circuit applications. The ability to directly monitor and control the ion beam dose and energy during implantation gives this technique precision that cannot be achieved in a diffusion furnace. It is this precision that makes ion implantation more attractive than a bAtch furnace process where many wafers at a time can be doped. Some applications such as threshold control are possible by ion implantation, but are not practical through diffusion. Because of this precision in energy and dose control, ion implantation in the megavolt regime has potential to replace chemical-vapor-deposition (CVD) epitaxial growth for the formation of buried dopant l
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