Metalorganic chemical vapor deposition of titanium oxide for microelectronics applications
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John J. Sullivan and Bin Han MKS Instruments, Incorporated, Andover, Massachusetts 01810 (Received 7 August 2000; accepted 3 April 2001)
A chemical vapor deposition process has been developed for titanium dioxide (TiOx) for applications as capacitor dielectric in sub-quarter-micron dynamic random-access memory devices, and as gate insulators in emerging generations of metal-oxide-semiconductor transistors. Studies using the -diketonate source precursor (2,2,6,6-tetramethyl-3,5-heptanedionato) titanium were carried out to examine the underlying mechanisms that control film nucleation and growth kinetics and to establish the effects of key process parameters on film purity, composition, texture, morphology, and electrical properties. Resulting film properties were thoroughly analyzed by x-ray diffraction, x-ray photoelectron spectroscopy, Rutherford backscattering spectrometry, scanning electron microscopy (SEM), focused-ion-beam SEM, and capacitance–voltage (C–V) measurements. The study resulted in the identification of an optimized process for the deposition of an anatase–rutile TiOx film with a dielectric constant approximately 85 at 1 MHz for a 330-nm thickness, and a leakage current below 2 × 10−8 A/cm2 for bias voltage values up to 3.5 V.
I. INTRODUCTION
Emerging generations of sub-quarter-micron dynamic random-access memory (DRAM) devices are predicted to exhibit a gradual decrease in individual cell size as memory capacity increases from 256 Mbit to 16 Gbit.1 The reduction in cell size will occur in spite of the need to maintain a constant cell capacitance across multiple DRAM device generations, such as 25 fF/m2 for the 1 and 4 Gbit DRAM device generations.2 This steady trend towards higher device density and reduced cell size places severe constraints on DRAM design rules and drives the need for innovative architectural schemes that accommodate the placement of an ever-expanding number of capacitors into the smallest overall chip area possible. Two architectural approaches are being considered to solve this problem. One approach involves the development of innovative stack and trench structures that increase the storage area per capacitor without expanding the corresponding cell area.3 A second approach focuses on replacing the current silicon nitride (SiNx)–silicon oxide (SiO2) dielectric material system, where the a)
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J. Mater. Res., Vol. 16, No. 6, Jun 2001 Downloaded: 25 Mar 2015
individual constituents exhibit dielectric constants of ⑀SiO2 ∼ 3.9 and ⑀Si3N4 ∼ 7, with a dielectric material having a substantially higher permittivity and lower leakage current characteristics.3 The second approach is also mandated by the continuous reduction in cell area, which has driven the thickness of the oxide and nitride–oxide (NO) systems down to the physical limit (5 nm) of the effective SiO2 thickness.4 The minimum acceptable thickness of the NO dielectric is considered to be around 3.5 to 4.0 nm in oxide equivalent thickness. Belo
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