Modeling Method for Development of Digital System Algorithms Based on Programmable Logic Devices
- PDF / 122,700 Bytes
- 8 Pages / 594 x 792 pts Page_size
- 107 Downloads / 221 Views
MODELING METHOD FOR DEVELOPMENT OF DIGITAL SYSTEM ALGORITHMS BASED ON PROGRAMMABLE LOGIC DEVICES O. O. Letychevskyi,1† V. S. Peschanenko,2 V. S. Kharchenko,3 V. A. Volkov,1‡ and O. M. Odarushchenko4
UDC 004.05, 004.42
Abstract. The paper deals with state-of-the-art trends in the field of automated hardware development, specifically development of digital systems using programmable logic integrated circuits, as exemplified by field-programmable logic arrays. The paper suggests a modeling method of development using an algebraic model of design specifications, requirements and binary codes in order to apply formal methods of verification, model-based testing, as well as methods of algebraic matching. The specifications of the algebraic hardware model are behavior algebra determined on a set of actions and behaviors. Keywords: field-programmable gate arrays, symbolic modeling, algebraic matching, behavior algebra. INTRODUCTION The modeling method of development provides for using models of different abstraction levels at each phase of hardware or software system development. Application of this approach greatly increases the possibilities of design automation, thus leading to significant increase in the system reliability and allowing for optimization of the system testing, its formal verification, and conformance checking. This paper discusses the process of digital system development using a programmable logic device (PLD), and in particular its variation known as FPGA (Field-Programmable Gate Array) [1]. In order to design a FPGA-based digital system, a well-defined process of developing the system along with its components is implemented. Different models of development life cycle are used in accordance with the respective sequence and requirements of the standards. The process of FPGA-based critical system development relies on the so-called V model [2], which consists of the phases specified in Fig. 1. At the phase of requirement engineering, the requirements are collected for the future device to be implemented based on a FPGA. The requirements can be collected as textual or tabular data to be used by the engineers and testers during the development. Although there is no special language for representing the requirements to the algorithms, automation of certain layers of high-level development and respective code generation from the requirement level is supported in Mathworks, Intel (HLS Compiler), and Xilinx (HDL coder). The design phase is to engineer the architecture of the future product and its components using HDL (Hardware Design Level) languages. Such languages include VHDL [3] and SystemVerilog [4]. 1
V. M. Glushkov Institute of Cybernetics, National Academy of Sciences of Ukraine, Kyiv, Ukraine, [email protected]; ‡[email protected]. 2Kherson State University, Kherson, Ukraine, [email protected]. 3M. E. Zhukovsky National Aerospace University “Kharkiv Aviation Institute,” Kharkiv, Ukraine, [email protected]. 4SPE “RadiCS” LLC, Kropyvnytskyi, Ukr
Data Loading...
