Programmable Logic
This chapter provides an overview of programmable logic devices (PLDs). The term PLD is used as a generic description for any circuit that can be programmed to implement digital logic. The technology and architectures of PLDs have advanced over time. A hi
- PDF / 1,219,859 Bytes
- 14 Pages / 504.567 x 720 pts Page_size
- 20 Downloads / 216 Views
scribe the basic architecture and evolution of programmable logic devices. Describe the basic architecture of field-programmable gate arrays (FPGAs).
11.1 Programmable Arrays 11.1.1 Programmable Logic Array (PLA) One of the first commercial PLDs developed using modern integrated circuit technology was the programmable logic array (PLA). In 1970, Texas Instrument introduced the PLA with an architecture that supported the implementation of arbitrary, sum of products logic expressions. The PLA was fabricated with a dense array of AND gates, called an AND plane, and a dense array of OR gates, called an OR plane. Inputs to the PLA each had an inverter in order to provide the original variable and its complement. Arbitrary SOP logic expressions could be implemented by creating connections between the inputs, the AND plane, and the OR plane. The original PLAs were fabricated with all of the necessary features except the final connections to implement the SOP functions. When a customer provided the desired SOP expression, the connections were added as the final step of fabrication. This configuration technique was similar to an MROM approach. Figure 11.1 shows the basic architecture of a PLA.
Fig. 11.1 Programmable logic array (PLA) architecture # Springer Nature Switzerland AG 2019 B. J. LaMeres, Introduction to Logic Circuits & Logic Design with Verilog, https://doi.org/10.1007/978-3-030-13605-5_11
383
384
•
Chapter 11: Programmable Logic
A more compact schematic for the PLA is drawn by representing all of the inputs into the AND and OR gates with a single wire. Connections are indicated by inserting X’s at the intersections of wires. Figure 11.2 shows this simplified PLA schematic implementing two different SOP logic expressions.
Fig. 11.2 Simplified PLA schematic
11.1.2 Programmable Array Logic (PAL) One of the drawbacks of the original PLA was that the programmability of the OR plane caused significant propagation delays through the combinational logic circuits. In order to improve on the performance of PLAs, the programmable array logic (PAL) was introduced in 1978 by the company Monolithic Memories, Inc. The PAL contained a programmable AND plane and a fixed-OR plane. The fixed-OR plane improved the performance of this programmable architecture. While not having a programmable OR plane reduced the flexibility of the device, most SOP expressions could be manipulated to work with a PAL. Another contribution of the PAL was that the AND plane could be programmed using fuses. Initially, all connections were present in the AND plane. An external programmer was used to blow fuses in order to disconnect the inputs from the AND gates. While the fuse approach provided one-time-only programming, the ability to configure the logic post-fabrication was a significant advancement over the PLA, which had to be programmed at the manufacturer. Figure 11.3 shows the architecture of a PAL.
11.1 Programmable Arrays
•
385
Fig. 11.3 Programmable array logic (PAL) architecture
11.1.3 Generic Array Logic (GAL) As the popularity of the PAL
Data Loading...
