New Contact Etch Process for Embedded DRAM Applications
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ABSTRACT For embedded DRAM (E-DRAM) devices with feature sizes of 0.25 jLm and beyond, contact processes with low contact resistance and low junction leakage current are required. The contact etch process needs to etch through multi-layer structures with SiO 2, SiON/SiN layers and stop on Ti-polycide gate and Ti-salicide active regions at the same time. The key issues include high selectivity to TiSix, vertical profile, complete removal of SiON/SiN cap layer and no polymer residues. In this paper, multi-layer contact etching without attacking TiSix is reported. Using new process chemistry, the new contact etch process has been demonstrated for the manufacturing of 0.25 jim E-DRAM and beyond.
INTRODUCTION Combining Logic and dynamic random access memory (DRAM) circuits in a chip, embedded DRAM can increase the number of data lines between the DRAM blocks and logic portion to as many as 1024 or more. This approach provides advantages of high bandwidth between memory and logic, low power consumption, smaller footprint and higher performance of the chip [1]. Minimizing process steps, forming thermally stable dual work function gates and implementing a salicide process in the DRAM process are essential to merge DRAMs and CMOS Logic [2]. This unique process requires challenging contact etching to etch through multi-layer dielectric structures and stop on Ti-polycide gates and salicided active regions. The conventional contact etch process with fluorocarbon (CxF 2x+2) and 0 2/CO/Ar chemistry can not etch through SiN/SiON and stop on TiSix film with high selectivity [3,4]. It usually stops on both TiSix and SiN or etches through both films. In this paper, a new process has been developed to selectively etch SiN/SiON without attacking TiSix at the same time. The high etch selectivity to the TiSix layer is attributed to the formation of C-rich polymer [5]. To selectively etch the SiN/SiON layers, the presence of H-containing species becomes critical [6]. In this paper, etching results of C4 F5/CO/Ar chemistry with the addition of H-containing gases, e.g., CH 2F2, CH 3F, CHF 3, C2H2F4 , C3H2 F6, etc. will be discussed. To determine device performance, contact resistance and junction leakage current were measured. The electrical data showed that TiSix loss, etch profile and polymer removal/cleaning are the key factors. The mechanism and the correlation between electrical characteristics and process parameters will be discussed. 177 Mat. Res. Soc. Symp. Proc. Vol. 564 © 1999 Materials Research Society
EXPERIMENT A 0.25 jtm E-DRAM device was used in this study as a vehicle for process verification. The device structure and process sequence for the contact etch process are described in Figs. I and 2, respectively. An interlayer dielectric (ILD) layer was first deposited and planarized by CMP. The contacts were defined by lithography and etch steps. Optional N+ and P+ plug implants followed, depending on device requirements. Then the contact glue layer and metal were deposited to form contact plugs. Both Magnetron Reactive Ion
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