Non-idealities in Graphene/ p -silicon Schottky-barrier Solar Cells
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Non-idealities in Graphene/p-silicon Schottky-barrier Solar Cells Derek Y.T. Lin, Shabnam Shambayati, Nima Mohseni Kiasari, David L. Pulfrey, Peyman Servati Department of Electrical and Computer Engineering, University of British Columbia, 2332 Main Mall, Vancouver, BC V6T 1Z4, Canada ABSTRACT This paper presents fabrication details and preliminary experimental results for graphene/p-silicon Schottky-barrier solar cells, where graphene is used as a transparent electrode and forms a rectifying junction with silicon wafer. Deviations from expected Schottky behavior in the form of large diode-ideality factors and s-shaped current-voltage curves observed in measurements are reported and analyzed. INTRODUCTION Schottky-barrier junctions are potentially easier and cheaper to fabricate in comparison to p-n junction devices; so they are of interest for cost-sensitive devices such as solar cells. Graphene films are nominally appropriate as a transparent electrode material for Schottky-barrier solar cells due to their high optical transparency [1], low sheet resistance [2], and tunable work function [3-5]. Achievable values of work function appear to range from 4.3 eV [4] to 4.9 eV [5]. There have been reports of graphene/n-Si Schottky-barrier devices [6], but here we use p-silicon as it should yield higher barrier heights [7], which, in turn, should lead to lower dark currents and higher open-circuit voltages. Our preliminary results show reasonable values for the open-circuit voltage, but the s-shaped form of the illuminated I-V characteristic gives very low fill-factors. We speculate on the reasons for this and for the occurrence of high ideality factors in our diodes. EXPERIMENTAL DETAILS Schottky photovoltaic devices are fabricated on a 3” p-type silicon wafer with 300 nm of silicon dioxide (SiO2). After standard RCA cleaning, electrode patterns are created using photolithography on the top side of the wafer. Then, 5nm of chromium and 100nm of gold are evaporated, followed by lift off to create the top contacts for the solar cell. By coating the top surface with a photoresist, a 10:1 buffered oxide etch is used to etch away the SiO2 on the bottom, followed by evaporation of 100nm of aluminum on the back of wafer for creation of the back contact. Graphene flakes are peeled from the bulk of highly oriented pyrolytic graphite (HOPG) and transferred to the substrate by the scotch tape transfer method [8]. This process is repeated until a few graphene flakes are identified under optical microscopy by a slight shift in color, as shown in Figure 1. P-type silicon is used as the substrate as it offers the possibility of a higher Schottky barrier height and, therefore, a lower dark current and a higher open-circuit voltage than n-type silicon [7]. HOPG is used because its contact causes minimal disturbance at the semiconductor surface. This is because the van der Waals force of attraction is relatively weak and the graphene sheets of the graphite are robustly impervious to diffusion of impurity atoms [9]. HOPG is also very stable
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