Non-lithographic Patterning of Oxide-Embedded Silicon Nanoparticles
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Non-lithographic Patterning of Oxide-Embedded Silicon Nanoparticles José R. Rodríguez Núñez1, Melanie Johnson1, Jonathan G. C. Veinot1 1 Department of Chemistry, 11227 Saskatchewan Drive, University of Alberta, Edmonton, Alberta, T6G 2G2, Canada. ABSTRACT Oxide-embedded Silicon nanoparticles (OE-Si-NPs) are of great interest for many applications due to unique size effects observed when their size drops below 5 nm (Silicon’s Bohr exciton radius). Some of the suggested applications require patterning of the nanoparticles in an ordered array. Lithographic methods to pattern Si-NPs are common in the literature, however these methods can be costly, and are not time-efficient. Recently, non-lithographic patterning techniques have become very attractive because they are cost-effective and straightforward. In this proceeding we will demonstrate non-lithographic patterning of OE-SiNPs characterized via AFM and XPS. INTRODUCTION Semiconductor nanocrystals are of great interest due to their quantum confined luminescence.1 II-VI and III-V direct bandgap quantum dots (QDs) paved the way for the development of synthesis and characterization techniques to understand and manipulate the interesting optical and material properties of 0-dimensional nanostructures.2 Many applications have been suggested for the aforementioned QDs, from solar cell sensitizers, to cellular probes, to lasing, among others.3-5 Although these materials laid the ground work for, and in many respects still lead the semiconductor nanocrystal field, the associated toxicity of these systems is of great concern.6 Group IV semiconductors (e.g., silicon) are non-toxic and are thus generating increased interest as materials suitable for day-to-day consumer applications.7, 8 Many QD applications require patterning techniques to be developed if full material functionality is to be realized. For example, solid state memory devices commonly known as FLASH memory require nanoparticles to be embedded in an orderly fashion in a gate dielectric layer.9 This structure yields devices characterized by low-voltage operation as well as improved scalability and retention properties. Methods such as chemical vapour deposition (CVD), atomic layer deposition (ALD) and physical vapour deposition have been used to fabricate patterned silicon nanostructures.10 Such physical and lithographic patterning techniques however can be costly, require specialized personnel and cannot pattern large areas efficiently. Alternatively, block-copolymer (BCP) patterning (a non-lithographic technique) is a cost effective, straightforward method that can create regular patterns over large areas.9 Although BCP patterning can only yield a limited set of geometries, its importance is exemplified by the integration of BCP self-assembly processes into a semiconductor fabrication facility at IBM Thomas J. Watson Research Center in New York.11 Reports of BCP patterning of semiconductor materials are numerous, however these contributions focus on Group II-VI materials.10 Literature concerning BCP patterning of
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