Novel Epoxy Siloxane Polymer as Low-K Dielectric
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NOVEL EPOXY SILOXANE POLYMER AS LOW-K DIELECTRIC Pei-I Wang*, Jasbir S. Juneja*, Shyam Murarka*, Toh –Ming Lu*, Ram Ghoshal**, and Rajat Ghoshal** *Center of Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY **Polyset Co. Inc., Mechanicville, NY ABSTRACT This paper introduces a low-k dielectric material, a novel epoxy siloxane polymer, made by Polyset Co. Inc, which has promising properties. The polymer was spin-deposited, and thickness and optical properties were measured using variable-angle spectroscopic ellipsometry (VASE). Fourier transform infrared (FTIR) spectra of as deposited and cured polymers showed that the polymer is fully cured at 165 °C. The low curing temperature of the polymer lowers stress in back-end-of-line (BEOL) stack and thus improves the reliability. The polymer is thermally stable up to 400 °C. The polymer has Young’s modulus of ~5 GPa and hardness of greater than 0.4 GPa. After multiple stress cycles up to 300 °C, the residual stress in the polymer at room temperature is less than 60 Mpa. The polymer has good adhesion with semiconductor and dielectrics such as Si, SiC, and SiO2, metals such as Al, Cu, Co, and W, and barrier materials such as TaN. The bulk dielectric constant of the polymer is 2.4 - 2.7. The leakage current density in the polymer at the applied electrical field of 1 MV/cm is in 10-9 A/cm2 range and the breakdown field of the polymer is ranging from 5 to 7 MV/cm. The polymer when subjected to bias-temperature stress (BTS) conditions of 150 °C and 0.5 MV/cm shows no C-V shift for up to 100 min indicating that the polymer resists Copper diffusion. The current density under stress conditions of 150 °C and 0.5 MV/cm was less than 10-9 A/cm2 for up to 7 hrs. INTRODUCTION The speed of the logic devices is governed by the transistor gate delay, which is proportional to the size of the transistor, and the interconnect signal delay, characterized by the resistancecapacitance (RC) time constant. With the reductions in the dimensions of the devices below 0.18 micron, the interconnect delay has become the limiting factor.1 The drive in the industry is to replace the aluminum-SiO2 interconnects by copper-low-k. The industry has shifted to Cu technology but is still struggling to implement inter-layer dielectric (ILD) using low-k.2 The electrical, mechanical and chemical property requirements of the candidate ILD low-k materials are very stringent.3,4 At the same time, thermal budget is of concern for the semiconductor industry leading to the requirement of low k dielectric materials that can be processed at low temperatures. In addition, high temperature stability in the range of 400 °C of processed dielectric films is necessary to ensure circuit reliability.5 In addition to the inherent properties of the dielectric, compatibility with the current copper technology is a must for any candidate low k material. Copper ion injection in dielectric results in high leakage and premature failure.6 A diffusion barrier is required in between metal and dielectric to avoid me
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