Novel SVPWM technique for three-level T-type Z-source inverters
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ORIGINAL ARTICLE
Novel SVPWM technique for three‑level T‑type Z‑source inverters Satwant Singh1 · Santosh Sonar1 Received: 22 April 2020 / Revised: 25 November 2020 / Accepted: 27 November 2020 © The Korean Institute of Power Electronics 2020
Abstract In this paper, a new SVPWM switching technique, named ZSVM_1TI, has been proposed for a three-level (3L) T-type Z-source inverter (ZSI). ZSVM_1TI is based on three main modifications of the existing PWM techniques for 3L inverters. First, the existing SVPWM of a 3L ZSI has been modified to double the frequency of the null interval. After that, an improved version of the maximum boost control (MBC) has been proposed based on modified SVPWM to eliminate the problem of the sixth frequency ripple components of inductor current with the existing MBC technique of ZSIs. Finally, a new switching pattern of a reduced common-mode voltage (CMV) PWM technique has been proposed to increase the switching frequency of the impedance network so that the size of the passive elements can be reduced. The proposed ZSVM_1TI has been compared with the existing PWM technique in terms of the size of the impedance network, the dc-link utilization, and the inductor current ripple profile. The above-mentioned findings have been successfully validated using theoretical analysis, simulations, and experimental results. Keywords Common-mode voltage (CMV) · Maximum boost control · Space vector pulse width modulation (SVPWM) · Three-level T-type Z-source inverter
1 Introduction The topology of a three-level (3L) T-type inverter [1] is popular in low/medium power applications because of its attractive features when compared to the neutral point clamped 3L inverter. These features are the absence of clamping diodes, reduced switching and conduction losses, reduced gating circuit requirements, and compact size. Furthermore, the concept of the Z-source inverter (ZSI) [2] adds some more features to the existing topologies of two/ multilevel VSIs. These features are single-stage buck-boost operation and the elimination of the dead time between the inverter switches. Impedance network-based 3L buck-boost inverter topologies present in the literature are: Z-source/ QZ-source inverters [3–13], the LC switching-based neutral point clamped inverter in [14], the LCCT-derived 3L * Santosh Sonar [email protected] Satwant Singh [email protected] 1
Department of Electrical and Instrumentation Engineering, Thapar Institute of Engineering and Technology, Patiala, Punjab, India
inverter in [15], and switched boost inverters [16–18]. The major fields of research in the area of impedance source inverters include increased boost factor topologies [9, 19], reduced common-mode voltage (CMV) PWM techniques [3, 10, 11], neutral point capacitor voltage balancing algorithms [6, 8, 11], reduced capacitor stress topologies [12], and topologies with a reduced number of components [19, 20], etc. The T-type ZSI topology has been studied in [8, 10, 11] from the perspective of neutral point capacitor voltage
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