Offset Reduction Techniques in Highspeed Analog-To-Digital Converters
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and foldi
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ANALOG CIRCUITS AND SIGNAL PROCESSING SERIES Consulting Editor: Mohammed Ismail. Ohio State University
For other titles published in this series, go to www.springer.com/series/7381
OFFSET REDUCTION TECHNIQUES IN HIGHSPEED ANALOG-TO-DIGITAL CONVERTERS Analysis, Design and Tradeoffs
PEDRO M. FIGUEIREDO MIPSABG Chipidea JOÃO C. VITAL MIPSABG Chipidea
Pedro M. Figueiredo Chipidea Microeletrónica Av. Dr. Mário Soares 33 2740-119 Porto-Salvo Taguspark, Portugal [email protected]
ISBN: 978-1-4020-9715-7
João C. Vital Chipidea Microeletrónica Av. Dr. Mário Soares 33 2740-119 Porto-Salvo Taguspark, Portugal [email protected]
e-ISBN: 978-1-4020-9716-4
Library of Congress Control Number: 2008942088 © Springer Science + Business Media B.V. 2009 No part of the work may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written permission from the Publisher, with the exception of any material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by purchaser of the work. Printed on acid-free paper. 987654321 springer.com
To Patrícia and Gonçalo
Contents
Preface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi List of Symbols and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . xv 1.
HIGH-SPEED ADC ARCHITECTURES . . . . . . . . . . . . . . . . 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.2 The Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . .2 1.2.1 1.2.2 1.2.3
Basic Operations and Transfer Function . . . . . . . . . . . . . . . . . . . . . 2 Static Characterization of ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Dynamic Characterization of ADCs . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.3.1 1.3.2 1.3.3
Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Design Specifications of Each Building Block . . . . . . . . . . . . . . . . . 10 The Interpolation Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Two-Step Flash ADCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.4.1 1.4.2
Two-Step Flash ADC with DAC and Subtractor . . . . . . . . . . . . . . 17 Two-Step Subranging Flash ADC . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 Folding and Interpolation ADCs . . . . . . . . . . . . . . . . . . . . . . . . . 22 1.5.1 1.5.2 1.5.3
Architecture Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Cascaded Folding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Design Specifications of Each Building Block . . . . . . . . . . . . . . . . . 33
1.6 Building Blocks of CMOS High-Speed ADCs . . . . . . . . . . . . . . . . 38 1.6.1 1.6.
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